ADC1*
16
OUTPUT: Binary data 2
1
ADC2*
18
OUTPUT: Binary data 2
2
ADC3*
20
OUTPUT: Binary data 2
3
ADC4*
22
OUTPUT: Binary data 2
4
ADC5*
24
OUTPUT: Binary data 2
5
ADC6*
26
OUTPUT: Binary data 2
6
ADC7*
15
OUTPUT: Binary data 2
7
ADC8*
17
OUTPUT: Binary data 2
8
ADC9*
19
OUTPUT: Binary data 2
9
ADC10*
21
OUTPUT: Binary data 2
10
ADC11*
23
OUTPUT: Binary data 2
11
ADC12*
25
OUTPUT: Binary data 2
12
ADC13*
13
OUTPUT: Binary Data 2
13
ENDATA*
4
INPUT (Enable Data): Used to enable the tri-
state buffers driving the 14 bits of data onto the
output lines ADC0* through ADC13*.
READY*
10
OUTPUT (Data Ready): Indicates that data is
available for transfer to the MCA. READY*
will be reset after receipt of signal ACEPT*.
ACEPT*
2
INPUT (Data Accepted): Signals the ADC that
the data has been accepted by the MCA.
ACEPT* may reset when READY* resets
(handshake).
ENC* or
ENC
8
INPUT (Enable Converter): This signal en-
ables or disables the 9660 DSP. Enable/Disable
polarity is programmed with selection of MCA
type through the MCA menu.
CDT* or
CDT
6
OUTPUT (Composite Dead Time): This signal
indicates the time when the 9660 is busy and
cannot accept another input event. Enable/Dis-
able polarity is programmed with selection of
MCA type through the MCA menu.
BCB*
33
OUTPUT: Provides a negative true logic sig-
nal, approximately 250 ns wide; initiated by
PK Detect and conclusion of PUR guard. This
signal is required by the Model 599 LFC Mod-
ule.
User’s Manual - ICN 9231014G
79
Data Connector
