Document type:
Title:
Revision date:
Revision:
User's Manual (MUT)
Mod. V977 16 Channel I/O Register (Status A)
27/08/2004
1
NPO:
Filename:
Number of pages: Page:
00118/01:V977X.MUTX/01
V977_REV1.DOC
21
3
TABLE OF CONTENTS
1.
OVERVIEW ............................................................................................................................................................................5
1.1.
M
ODULE DESCRIPTION
.................................................................................................................................................5
2.
SPECIFICATIONS ...............................................................................................................................................................6
2.1.
P
ACKAGING
...................................................................................................................................................................6
2.2.
E
XTERNAL COMPONENTS
............................................................................................................................................6
2.3.
I
NTERNAL COMPONENTS
..............................................................................................................................................7
2.4.
P
OWER REQUIREMENTS
...............................................................................................................................................7
2.5.
T
ECHNICAL SPECIFICATION TABLES
..........................................................................................................................7
2.6.
F
RONT
P
ANEL
................................................................................................................................................................8
3.
OPERATING MODES .........................................................................................................................................................9
3.1.
F
UNCTIONAL DESCRIPTION
.........................................................................................................................................9
3.1.1.
I/O register mode ........................................................................................................................................... 10
3.1.2 .
Multihit pattern unit mode............................................................................................................................ 10
3.1.3.
Test channel .................................................................................................................................................... 11
3.2.
OR
LOGIC
.....................................................................................................................................................................12
3.3.
I
NTERRUPTER CAPABILITY
........................................................................................................................................12
4.
VME INTERFACE ............................................................................................................................................................ 14
4.1.
A
DDRESSING CAPABILITY
.........................................................................................................................................14
4.2.
D
ATA TRANSFER CAPABILITY
...................................................................................................................................14
4.3.
I
NPUT SET REGISTER
...................................................................................................................................................15
4.4.
I
NPUT MASK REGISTER
...............................................................................................................................................16
4.5.
I
NPUT READ REGISTER
...............................................................................................................................................16
4.6.
S
INGLE
-
HIT READ REGISTER
......................................................................................................................................16
4.7.
M
ULTI
-
HIT READ REGISTER
.......................................................................................................................................16
4.8.
O
UTPUT SET REGISTER
...............................................................................................................................................17
4.9.
O
UTPUT MASK REGISTER
...........................................................................................................................................17
4.10.
I
NTERRUPT MASK
.......................................................................................................................................................17
4.11.
O
UTPUT CLEAR REGISTER
..........................................................................................................................................17
