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User's Manual (MUT)
Mod. V977 16 Channel I/O Register (Status A)
27/08/2004
1
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00118/01:V977X.MUTX/01
V977_REV1.DOC
21
10
3.1.1. I/O register mode
The module operates as I/O register if the PATTERN bit of the CONTROL REGISTER is
set to 0 (default setting).
In this case the simplified channel scheme is shown in Fig. 3.2.
PATTERN = 0
OUTPUT
CH #n
to OR and IRQ
LOGIC
INPUT
CH #n
INPUT READ
VME REGISTER
INPUT
GATE
INPUT MASK
VME REGISTER
INPUT SET
VME REGISTER
CONTROL
REGISTER
GATE MASK BIT
D
Q
AR
1
SINGLE HIT READ
VME REGISTER
OUTPUT MASK
VME REGISTER
OUTPUT SET
VME REGISTER
CLEAR OUTPUT
VME REGISTER
INPUT
CLEAR
AR
Fig. 3.2: I/O register mode
In this operating mode the output of one channel is active when a single hit (from front
panel or VME generated) is received. The output can also be set by a write access to the
OUTPUT SET REGISTER.
The outputs can also be masked, individually for each channel, through the OUTPUT
MASK REGISTER.
In this operating mode, the two channel LEDs identify the channel status in the following
way:
Left LED: input signal active;
Right LED: output signal active.
3.1.2. Multihit pattern unit mode
The module operates as multihit pattern unit if the PATTERN bit of the CONTROL
REGISTER is set to 1.
In this case the simplified channel scheme is shown in Fig 3.3.
