Caen V2495, User Manual

Page: 44 / 62

CAEN
Electronic Instrumentation
UM5175 – V2495/VX2495 User Manual rev. 1
44
A data prefetch mechanism, implemented in the MFPGA, stores User data into a MFPGA local data queue (prefetch
data queue). The MFPGA prefetch queue data is available for readout over the VME or USB interface (see Sect.
Address
Map ).
The prefetch mechanism is illustrated by Fig. 10.4 .
nADS
LAD
WnR
nBLAST
nREADY
MAIN
FPGA
USER
FPGA
LOCAL BUS
LOCAL
BUS
MASTER
LOCAL
BUS
SLAVE
PREFETCH
DATA
QUEUE
USER
DATA
QUEUE
Fig. 10.4: Prefetch mechanism
Prefetch read cycles are initiated by the UFPGA logic: nREADY local bus signal must be used by the User logic to request
a new data prefetch cycle by the local bus master (MFPGA): The request is active when the nREADY is low. The local
bus master should have an internal prefetch queue (FIFO component). If a user request is pending and the local bus
master has available space into the prefetch queue, it will start an internal block transfer from local bus address
0x0000 (fixed). The User logic is required to respond only to address 0x0000: data from its data queue are made
available to the V2495 local bus. If a new register access is requested to the local bus master while a prefetch cycle is
ongoing, the prefetch cycle will be interrupted by asserting the nBLAST signal and the register access will be served
with priority. At the end of a register access, the user logic can keep the nREADY signal active to request a new prefetch
cycle to the LBM, which will fetch new data in its queue.
Please refer to the lb_int.vhd source code in the User demo firmware projects.: it is a Local Bus slave implementation
provided by CAEN as a reference.
The lb_int.vhd found in the Pattern Recorder demo firmware (see Sect.
Pattern Recorder Demo Description ) is a
demonstration of user logic implementation of the data prefetch mechanism.