CAEN
Electronic Instrumentation
UM5175
–
V2495/VX2495 User Manual rev. 1
40
10.2
User FPGA I/O ports
This section illustrates the I/O ports of the UFPGA. Port names are the same of the VHDL entity top-level ports used in
the template and demo firmware.
➢
Clock:
The user FPGA receives the board system clock
SIGNAL NAME
WIDTH
TYPE
DESCRIPTION
CLK
1
Input
50 MHz system clock
Tab. 10.1:
Clock ports description table
➢
Mainboard Robinson Nugent connector ports:
the ports A and B are input only. They feature 32 input channels that
reach the UFPGA as 32 single-ended LVTTL lines (3.3 V).
SIGNAL NAME
WIDTH
TYPE
DESCRIPTION
A
32
Input
A port values
B
32
Input
B port values
C
32
Output C port value
Tab. 10.2:
Mainboard Robinson-Nugent connector description table
➢
LEMO ports:
each of the LEMOs on the front panel can be used as input or output. The signals used are the
following:
SIGNAL NAME
WIDTH
TYPE
DESCRIPTION
GIN
2
Input
Input values for G0, G1
GOUT
2
Output Output values for G0, G1
SELG
Output
NIM/TTL selector
0 = NIM
1 = TTL
nOEG
Output Output enable (active low) (0=output, 1=input)
Tab. 10.3:
LEMO G ports description table
It should be noted that the ports G0, G1 can be set as inputs in two different ways:
•
By setting nOEG=1 and driving the LEMO inputs. In this way both ports will be used as inputs; their status can be
read from GIN[0] and GIN[1].
•
By setting to 0 both nOEG and the output signal of the input port and enabling the related 50 Ohm termination
(see Chap.
). In this way it is possible to force a logic level without damaging the output and to use one port as
an input and the other as an output.
Example
: G0 input, G1 output
nOEG=0
GOUT[0]=0
Enable the 50 Ohm G0 termination
In this way, it is possible to provide an input on the G0 channel, while having an output on the G1 port (through the
GOUT[1] signal). Note that in this configuration G1 should not be externally forced, as this might damage the input
circuit.
The 50 Ohm termination should also be enabled when a NIM input is provided (instead of a TTL). When the NIM logic
level is chosen the logic levels are inverted with respect to the TTL case: It is up to the firmware to handle this
inversion, for example using the SELG signal to invert the logic level as shown in the following VHDL assignment:
GIN_MOD <= GIN[0
] when SELG=’1’ else not GIN[0];
