PreDAC User’s Manual
24
A brief description of the binary flags in the internal status register of the
PreDAC is hereafter presented:
-
PreDAC in Slave mode (bit 15):
this bit is set when PreDAC is controlled by
the BEST system.
-
External interlock enabled (bit 14):
this bit is set when the external interlock
input is enabled (see MAX Command section);
-
Trigger mode enabled (bit 13):
this bit is set when the “trigger mode” is enabled
(see TRG Command section);
-
Gate mode enabled (bit 12):
this bit is set when the “gate mode” is enabled (see
GATE Command section);
-
Channel Status (bits 11-8):
these bits indicate if the corresponding output
channel is active or it is disabled (it’s output voltage is set to 0 V);
-
General fault (bit 7):
this bit is set if the module has experienced a fault – e.g.
generated by an external interlock or an internal protection trip (like internal
over-temperature). This bit is a logical ‘OR’ of all other fault flags and it is
latching – i.e. when a fault occurs, this bit is set together with the specific fault
bit. When a fault is detected, the module switches off all output channels. A
status reset of the device is necessary in order to reset the module (see the
following section);
-
Over-temperature fault (bit 1):
this bit is also latching and it is set when the
internal PreDAC temperature rises above the 50°C threshold; to reset this flag
it is necessary to execute a status reset command (see following section);
-
External interlock fault (bit 0):
this bit is set when the external interlock signal
is enabled and the input interlock signal is high (see Interlock and general I/O
connector section); to reset the flag the it is necessary to execute a status reset
(see the following section).
The internal status register can be read with the “STATUS:?
\r\n
” command. The
reply from the PreDAC unit to this command is in the format “STATUS:
value
\r\n
”,
where
value
is the ASCII representation of the internal status register value, composed
by 4 hexadecimal digits – corresponding to the 2-byte wide status register (every byte
is represented by two hexadecimal digits).
If at least one of the fault conditions occurs, then the respective bit and the
general fault bit are set simultaneously. The output voltages are set to a zero voltage
level in this conditions and it is not possible to enable them until the internal status
register is reset.
The command to reset the fault condition of the status register is
“STATUS:RESET
\r\n
”; the PreDAC unit replies to this command with an
acknowledgment string.
Summary of Contents for PreDAC
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