15
PMCCTR32
Copyright
2001 BVM Ltd.
7.3.10 Counter/Timer Clock Source Register
The 8-bit write only Counter/Timer Clock Source Register where each bit corresponds to an individual
Counter/Timer (0 to 7). If the corresponding bit is set to 1 then the relevant Counter/Timer clock input
is driven from the internal clock otherwise the clock input is driven from the external clock - see
section "7.3.2 Counter/Timer Clock Register (on page 14)".
7.3.11 Direction
Register
The 8-bit read only Direction Register where each of the least significant four bits correspond to a
group of 8 I/O bits. If the corresponding bit is set to 1 the bit is an output otherwise it is an input.
Reserved bits (RSVD) read as zero.
7
6
5
4
3
2
1
0
RSVD
RSVD
RSVD
RSVD
0
0
0
1
7.3.12 Function
Register
The 8-bit read only Function Register contains the low byte of the PCI Subsystem Device ID - see
section "7.1 PCI Configuration Details (on page 13)". This can be used to determine the type of board
fitted from the PMCDIO and PMCCTR range.
7.3.13 Status & Control Register
The 16-bit read/write Status & Control Register is used to control a number of the module functions as
described below. Reserved bits (RSVD) read as zero and should be written as zero for future
compatibility.
7
6
5
4
3
2
1
0
WDGST
IWDEN
RSVD
GOPEN
WINEN
RSVD
RSVD
RSVD
15
14
13
12
11
10
9
8
RSVD
RSVD
RSVD
RSVD
RSVD
INCLK2
INCLK1
INCLK0
7.3.13.1 Watchdog Interrupt Enable (Bit 3: WINEN)
When set to 1 this bit enables the generation of a PCI Interrupt if an enabled internal watchdog times
out - see section "7.3.13.3 Internal Watchdog Enable (Bit 6: IWDEN) (below)". If clear no PCI Interrupt
will be generated.
7.3.13.2 Global Output Enable (Bit 4: GOPEN)
When set to 1 this bit enables all output signals. If clear all output signals are disabled. Input signals
are unaffected.
7.3.13.3 Internal Watchdog Enable (Bit 6: IWDEN)
When set to 1 the internal watchdog function is enabled and if the watchdog times-out then the
outputs will be disabled. If clear the state of the watchdog is ignored.
7.3.13.4 Watchdog Status (Bit 7: WDGST)
When set to 1 this bit indicates an enabled internal watchdog has timed-out - see section "7.3.13.3
Internal Watchdog Enable (Bit 6: IWDEN) (above)". Once set this bit cannot be cleared.
