PMCCTR32
14
Copyright
2001 BVM Ltd.
7.3 Register
Descriptions
7.3.1
Counter/Timer Output Register
The 8-bit read only Counter/Timer Output Register contains the levels of the Counter/Timer Output
pins on the logic device. When reading back the output signals, no account is taken of values beyond
the I/O buffers. The Counter/Timer Output pins go active when the count crosses the 0000/FFFF
boundary - active LOW or HIGH is selected in the Counter/Timer Output Control Register - see
section "7.3.8 Counter/Timer Output Control Register (below)".
7.3.2
Counter/Timer Clock Register
The 8-bit read only Counter/Timer Clock Register contains the levels of the Counter/Timer Clock pins
on the logic device. When reading back the output signals, no account is taken of values beyond the
I/O buffers. The Counter/Timer Clock pins are used to clock the Counter/Timer when the external
clock is selected in the Counter/Timer Clock Source Register - see section "7.3.10 Counter/Timer
Clock Source Register (on page 15)".
7.3.3
Counter/Timer Gate Register
The 8-bit read only Counter/Timer Gate Register contains the levels of the Counter/Timer Gate pins
on the logic device. When reading back the output signals, no account is taken of values beyond the
I/O buffers. The Counter/Timer Gate pins are used to enable the count: HIGH to enable; LOW to
disable. If the Counter/Timer Gate pins are not connected they default to LOW (disabled) and may be
overridden - see section "7.3.5 Counter/Timer Gate Override Register (below)".
7.3.4
Counter/Timer Direction Register
The 8-bit read only Counter/Timer Direction Register contains the levels of the Counter/Timer
Direction pins on the logic device. When reading back the output signals, no account is taken of
values beyond the I/O buffers. The Counter/Timer Direction pins are used to control the count
direction: HIGH for UP; LOW for DOWN. If the Counter/Timer Direction pins are not connected they
default to LOW (count down) and may be overridden - see section "7.3.6 Counter/Timer Direction
Override Register (below)".
7.3.5
Counter/Timer Gate Override Register
The 8-bit read/write Counter/Timer Gate Override Register where each bit corresponds to an individual
Counter/Timer (0 to 7). The bit is OR'ed with the corresponding gate input pin for the respective
Counter/Timer. If the gate input pin is left disconnected then it is a 0, therefore writing a 1 to the
corresponding bit in the Counter/Timer Gate Override Register will enable the Counter/Timer and
writing a 0 will disable the Counter/Timer.
7.3.6
Counter/Timer Direction Override Register
The 8-bit read/write Counter/Timer Direction Override Register where each bit corresponds to an
individual Counter/Timer (0 to 7). The bit is OR'ed with the corresponding direction input pin for the
respective Counter/Timer. If the direction input pin is left disconnected then it is a 0, therefore writing a
1 to the corresponding bit in the Counter/Timer Gate Override Register will cause the Counter/Timer to
count UP and writing a 0 will cause the Counter/Timer to count DOWN.
7.3.7
Counter/Timer Status Register
The 8-bit read/write Counter/Timer Status Register where each bit corresponds to an individual
Counter/Timer (0 to 7). If the corresponding bit is set to 1 then the relevant Counter/Timer output is
active - writing a 1 to the corresponding bit clears this state and clears the interrupt.
7.3.8
Counter/Timer Output Control Register
The 8-bit write only Counter/Timer Output Control Register where each bit corresponds to an
individual Counter/Timer (0 to 7). If the corresponding bit is set to 1 then the relevant Counter/Timer
output is active HIGH otherwise the output is active LOW.
7.3.9
Counter/Timer Interrupt Enable Register
The 8-bit read/write Counter/Timer Interrupt Enable Register where each bit corresponds to an
individual Counter/Timer (0 to 7). If the corresponding bit is set to 1 then the relevant Counter/Timer
interrupt is enabled and an interrupt will be generated when the output is active. The interrupt may be
cleared by writing a 1 to the relevant bit in the Counter/Timer Interrupt Enable Register or by clearing
the output - see section"7.3.7 Counter/Timer Status Register (above)".
