BVME310
Copyright
1997 BVM Ltd.
17
The DUART includes a 5 bit input port and 7 bit Output port, these bits are used for a number of
functions including Serial Port handshaking, EEPROM accesses and Sense bits. The port functionality
is listed below.
Input Port Usage:
IP0
-
CTS A.
IP1
-
CTS B.
IP2
-
Parallel Sense Bit.
IP3
-
Parallel Sense Bit.
IP4
-
Parallel Sense Bit.
IP5
-
Abort Monitor/Non-Volatile EEPROM Data Read.
Details of the parallel sense bits can be found in 5.2.5 JPRE Parallel Sense Block. Details of the IP5
functionality can be found 5.2.6 FL3 68681 IP5 Source in and 7.6 Non Volatile EEPROM .
Output Port Usage:
OP0
-
RTS A.
OP1
-
RTS B.
OP2
-
not used.
OP3
-
not used.
OP4
-
not used.
OP5
-
EEPROM Data Write.
OP6
-
EEPROM Chip Select.
OP7
-
EEPROM Clock.
Details of the EEPROM functionality can be found in 7.6 Non Volatile EEPROM.
For further information refer to the MC68681 Data sheet, see Appendix Appendix A.
7.6 Non Volatile EEPROM (451-48013 only)
The 451-48013 variant of the BVME310 provides a serial access 1024-bit electrically erasable PROM
(EEPROM) that is typically used to hold configuration data. The EEPROM is organized as 64x16-bit
registers. Each register is accessed by sending the READ instruction followed by the register address.
The 16-bits of data may then be read out.
The EEPROM is accessed by manipulation of the 68681's Output Port registers (OPR). Data bit 5, 6 and
7 (OP5:OP7) provide the EEPROM control, DIN, CS and CLK respectively. NB. The Output Register has
active low drivers so the sense of the bits are inverted. Bit 5 of the input port (IP5) provides the read data,
DOUT.
The DIN sequence to prepare for READing the EEPROM is:
CS=1 / 0 / 1 / 1 / 0 / A5 / A4 / A3 / A2 / A1 / A0
Where A5,A4,A3,A2,A1,A0 is the 6-bit register address and '/' = CLK high transition.
Subsequent CLK high transitions make D15 - D0 available on DOUT data bit. CS is brought low ( =0 )
after reading the data.
