BVME310
Copyright
1997 BVM Ltd.
5
3.6 Interrupts
3.6.1 VMEbus Interrupt Handler
The BVME310 will support VMEbus interrupts on any of 7 levels. A jumper link is provided to allow
each Interrupt level to individually enabled.
A VMEbus interrupt causes the CPU to reply with a VMEbus Master Interrupt acknowledge cycle. This
cycle uses only IACK that is broadcast in a similar way to the addresses. The A1, A2 and A3 address
lines indicate the address level being handled.
The interrupting device returns an ID vector on the odd data byte. This is used as the user vector by
the CPU.
3.6.2 Internal Interrupts
Internal CPU interrupts are generated from a variety of sources, as detailed in the table below:
Level
Source
Type
7
VME IRQ7
Abort Switch
ACFAIL
VBCLR
Autovectored
Autovectored
Autovectored
Autovectored
6
VME IRQ6
Vectored
5
VME IRQ5
Vectored
4
VME IRQ4
Vectored
3
VME IRQ3
68681 SERIAL
Vectored
Vectored
2
VME IRQ2
Vectored
1
VME IRQ1
Vectored
The table shows a number of Interrupt sources, these can be link configured to match the customers
requirements. VMEbus Interface
3.7 VMEbus Master
Byte or word Master accesses may be made to the standard (A24) and short (A16) address spaces.
Read Modify Write (RMW) cycles are supported.
The VMEbus daisy chain arbitration circuitry is optimised to allow very efficient multi-master operation.
Special purpose LSI provides immunity to metasability. Asynchronous arbitration gives BGIN to
BGOUT delay = 15nS worst case.
The BVME310 supports the Release When Done (RWD) VMEbus arbitration method. The method
uses FAIR requesting, ensuring each master has an equal chance of obtaining the bus.
