background image

Broadcom

ACPL-C740-EvalKit-UG100

6

ACPL-C740 Evaluation Kit Board

 User Guide 

Isolated Sigma-Delta Modulator

The shunt resistor mounting pad is designed to accommodate various shunt resistor package types. The Kelvin 
connection PCB trace connects from the center of the pad to the inputs of ACPL-C740 through the anti-aliasing filters 
(AAFs). Connecting from the center of the pads is usually the optimum location for most shunt resistor designs. The 
evaluation board also provides pads P1 and P2 for soldering thick cables to the motor driving board.

Apply an input voltage signal without a shunt resistor.
Connect the audio cable with the audio 3.5-mm jack connected to either a PC, smart phone, tablet, MP3 player, or any 
kind of audio player device. Then, connect the crocodile clips to the shunt resistor mounting pads.
Check the 1 kHz sine test signal and supply a 1 kHz sine wave voltage signal to the evaluation board. Other methods 
include playing any of the three provided sine wave files on a music player software program from the audio player 
devices described previously. Adjust the volume until the signal level is near ±200 mV or ±20,000 ADC counts for best 
SNR/SNDR performance.
The performance of SNR/SNDR is dependent on a few factors:
– The evaluation board
– The sigma-delta modulator used, in this case, the ACPL-C740
– Input signal frequency used
– The decimation ratio, which can be set at the application GUI to 256, 128, or 64.
– The input signal level. The ACPL-C740 recommended input voltage range is from –200 mV to 200 mV. To achieve 

the best SNR/SNDR, design the maximum input signal range nearest ±200 mV (using the selection of the input 
current range and shunt resistor value).

– The input signal source.

Table 2

 shows a comparison of the SNR/SNDR performance between audio signal sources coming from a laptop.

Table 2:  SNR/SNDR Comparison

Filter 
Configuration

Signal Source from Audio Jack of Laptop 

Signal Freq. = 500 Hz

Signal Freq. = 1000 Hz

Signal Freq. = 2000 Hz

SNR(dB)

SNDR(dB)

SNR(dB)

SNDR(dB)

SNR(dB)

SNDR(dB)

Sinc3 DR = 64

not enough sampling sinewave cycles

66

64

61

59

Sinc3 DR = 128

76

73

74

73

70

63

Sinc3 DR = 256

77

75

78

77

73

63

Summary of Contents for ACPL-C740

Page 1: ...tage as shown in Figure 1 A differential input signal of 0V ideally produces a data stream of ones 50 of the time and zeros 50 of the time A differential input of 200 mV corresponds to an 18 75 densit...

Page 2: ...ng items ACPL C740 evaluation board Cable with USB mini USB terminations Softcopy folder containing drivers and application software programs The softcopy folder contains the following document or sof...

Page 3: ...nce connected LED1 to LED4 light up in an undefined sequence to indicate that the board connections are properly done The C740 SDM EVBD and FPGA EVBD boards are shown respectively below 8 Go to the PC...

Page 4: ...erage signal levels are shown in the time domain in terms of either mV or ADC count SNR SNDR 2nd harmonic and 3rd harmonic levels are displayed in the frequency domain 1 Click Start to begin capturing...

Page 5: ...completion The FPGA LOAD Completed pop up appears as shown below 4 For quick help click Help from the top right corner of the application GUI then select the setup guide The help guide also describes...

Page 6: ...ee provided sine wave files on a music player software program from the audio player devices described previously Adjust the volume until the signal level is near 200 mV or 20 000 ADC counts for best...

Page 7: ...unt resistor until an input signal level of 200 mV is reached One such function generator is the ultra low distortion DS360 function generator from Standford Research Systems Table 3 shows the SNR SND...

Page 8: ...of the PE22100 is selected as 100 pF which results in a switching frequency of around 200 kHz This frequency is outside the operating bandwidth of the ACPL C740 sigma delta modulator and the Sinc3 fi...

Page 9: ...ng SW2 once If the problem arises perform a full board reset by pressing SW3 once Each evaluation board is functionally checked and tested before being sent to the customer If a problem continues to a...

Page 10: ...BER FOOTER RF1 Vdd1 10 uF C15 VDD1 1 VIN 2 VIN 3 GND1 4 GND2 5 MDAT 6 MCLK 7 VDD2 8 U1 ACPL C740 0R R8 GND1 GND1 GND2 P1 RSHUNT P2 RSHUNT 0R R9 0R R10 RUBBER FOOTER RF2 RUBBER FOOTER RF3 RUBBER FOOTER...

Page 11: ...om ACPL C740 EvalKit UG100 11 ACPL C740 Evaluation Kit Board User Guide Isolated Sigma Delta Modulator C740 SDM EVBD PCB Layout Figure 9 C740 SDM EVBD PCB Top Layer Figure 10 C740 SDM EVBD PCB Second...

Page 12: ...Broadcom ACPL C740 EvalKit UG100 12 ACPL C740 Evaluation Kit Board User Guide Isolated Sigma Delta Modulator Figure 11 C740 SDM EVBD PCB Third Layer Figure 12 C740 SDM EVBD PCB Bottom Layer...

Page 13: ...nloading FPGA Code For FPGA configuration via SPI only 1 2 FB2 1 2 FB1 470 R1 0 1 uF C2 GND2 27 R2 GND2 GND2 47 pF C11 GND2 27 R3 1 5K R6 0 47 uF C12 C34 GND2 0 1 uF C3 GND2 0 01 uF C1 GND2 1 2 DNM J1...

Page 14: ...133 GND 61 GND 118 GND 127 U5 XC3S250E GND2 FTDI_D2 FTDI_D3 FTDI_D4 FTDI_D6 FTDI_D7 FTDI_RD USER_IO3 FTDI_WR USER_IO5 FTDI_D1 USER_IO26 USER_IO27 USER_IO28 USER_IO6 USER_IO7 USER_IO8 USER_IO9 USER_IN3...

Page 15: ...Broadcom ACPL C740 EvalKit UG100 15 ACPL C740 Evaluation Kit Board User Guide Isolated Sigma Delta Modulator FPGA EVBD PCB Layout Figure 15 FPGA EVBD PCB Top Layer Figure 16 FPGA EVBD PCB Second Layer...

Page 16: ...Broadcom ACPL C740 EvalKit UG100 16 ACPL C740 Evaluation Kit Board User Guide Isolated Sigma Delta Modulator Figure 17 FPGA EVBD PCB Third Layer Figure 18 FPGA EVBD PCB Bottom Layer...

Page 17: ...ore information please visit www broadcom com Broadcom reserves the right to make changes without further notice to any products or data herein to improve reliability function or design Information fu...

Reviews: