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Broadcom ACPL-C740 User Manual Download Page 13

Broadcom

ACPL-C740-EvalKit-UG100

13

ACPL-C740 Evaluation Kit Board

 User Guide 

Isolated Sigma-Delta Modulator

FPGA-EVBD Schematic Diagram

Figure 13:  FPGA-EVBD Schematic Diagram (Part 1)

3V3OUT

6

USBDM

8

USBDP

7

RSTOUT#

5

XTIN

43

XTOUT

44

RESET#

4

EECS

48

EESK

1

EEDATA

2

TEST

47

AG

N

D

45

GN

D

9

GN

D

18

GN

D

25

GN

D

34

AD0

24

AD1

23

AD2

22

AD3

21

AD4

20

AD5

19

AD6

17

AD7

16

AC0

15

AC1

13

AC2

12

AC3

11

SI/WUA

10

BD0

40

BD1

39

BD2

38

BD3

37

BD4

36

BD5

35

BD6

33

BD7

32

BC0

30

BC1

29

BC2

28

BC3

27

SI/WUB

26

PWREN

41

AV

C

C

46

VC

C

3

VC

C

42

VC

C

IO

A

14

VC

C

IO

B

31

U2

FT2232D

GND2

GND2

VCC

8

NC

7

ORG

6

GND

5

CS

1

SK

2

DIN

3

DOUT

4

U3

93C56B

GND2

2.2K

R4

10K

R7

SW2

B3S-1000

EEPROM, 2 MHz, 128x16

FTDI_SI

27

R17

27

R16

FTDI_WR

FTDI_RD

FTDI_TXE

FTDI_RXF

FTDI_D0
FTDI_D1
FTDI_D2
FTDI_D3
FTDI_D4
FTDI_D5
FTDI_D6
FTDI_D7

SPI_PROG

150 5%

R13

GND2

FPGA_RESET

SPI_INIT

SPI_CSO_B

SPI_DIN

SPI_MOSI

SPI_CLK

10K 5%

R28

3V3X

0.1 uF

C39

GND2

3V3X

2.2K

R5

I/O Set

 at

3.3V

0.01 uF

C8

GND2

0.1 uF

C6

Downloading
FPGA Code

For FPGA configuration via
SPI only.

1

2

FB2

1

2

FB1

470

R1

0.1 uF

C2

GND2

27

R2

GND2

GND2

47 pF

C11

GND2

27

R3

1.5K

R6

0.47 uF

C12

+

C34

GND2

0.1 uF

C3

GND2

0.01 uF

C1

GND2

1

2

DNM

J1

GND2

PORTVCC

5VIN

0.1 uF

C5

0.1 uF

C10

GND2

+

C33

GND2

VCCSW

USER_IN0
USER_IN1
USER_IN2
USER_IN3
USER_IN4
USER_IN5
USER_IN6
USER_IN7
USER_IN8

USER_IO0
USER_IO1
USER_IO2
USER_IO3
USER_IO4
USER_IO5
USER_IO6
USER_IO7
USER_IO8
USER_IO9
USER_IO10
USER_IO11
USER_IO12

USER_IO16
USER_IO17
USER_IO18
USER_IO19
USER_IO20
USER_IO21
USER_IO22
USER_IO23
USER_IO24
USER_IO25
USER_IO26
USER_IO27
USER_IO28

GND2

500mA 240-2390-2

MI0805K601R-10

5VCC

6 MHz

GND2

GND2

SW3
B3S-1000

GND2

5VCC

USER_IO13

GND2

4.7K

R24

4.7K

R23

5VCC

1

2

3

SW1
EG1218

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

DNM

USER_IO

H1

CR1

0.033 uF

C4

0.033 uF

C7

5VIN

UPLOAD

R22
10K

R40

0R

1

2

3

4

5

6

7

8

9

DNM

USER IN

H2

GND2

MCLK

MDAT

VDD2

5VCC

USER_IO0

USER_IN0

3V3X

0R

R18

0R

R19

0R

R20

1
2
3
4
5
6
7
8

J5

Header socket 1x8 RA

D-
D+

GND

5

ID

4

D+

3

D-

2

Vbus

1

Sh

ie

ld

SH

CN1

ZX62D-AB-5P8(30)

D

G

S

Q2

IRLML6402

RUBBER
FOOTER

RF1

RUBBER
FOOTER

RF2

RUBBER
FOOTER

RF3

RUBBER
FOOTER

RF4

Summary of Contents for ACPL-C740

Page 1: ...tage as shown in Figure 1 A differential input signal of 0V ideally produces a data stream of ones 50 of the time and zeros 50 of the time A differential input of 200 mV corresponds to an 18 75 densit...

Page 2: ...ng items ACPL C740 evaluation board Cable with USB mini USB terminations Softcopy folder containing drivers and application software programs The softcopy folder contains the following document or sof...

Page 3: ...nce connected LED1 to LED4 light up in an undefined sequence to indicate that the board connections are properly done The C740 SDM EVBD and FPGA EVBD boards are shown respectively below 8 Go to the PC...

Page 4: ...erage signal levels are shown in the time domain in terms of either mV or ADC count SNR SNDR 2nd harmonic and 3rd harmonic levels are displayed in the frequency domain 1 Click Start to begin capturing...

Page 5: ...completion The FPGA LOAD Completed pop up appears as shown below 4 For quick help click Help from the top right corner of the application GUI then select the setup guide The help guide also describes...

Page 6: ...ee provided sine wave files on a music player software program from the audio player devices described previously Adjust the volume until the signal level is near 200 mV or 20 000 ADC counts for best...

Page 7: ...unt resistor until an input signal level of 200 mV is reached One such function generator is the ultra low distortion DS360 function generator from Standford Research Systems Table 3 shows the SNR SND...

Page 8: ...of the PE22100 is selected as 100 pF which results in a switching frequency of around 200 kHz This frequency is outside the operating bandwidth of the ACPL C740 sigma delta modulator and the Sinc3 fi...

Page 9: ...ng SW2 once If the problem arises perform a full board reset by pressing SW3 once Each evaluation board is functionally checked and tested before being sent to the customer If a problem continues to a...

Page 10: ...BER FOOTER RF1 Vdd1 10 uF C15 VDD1 1 VIN 2 VIN 3 GND1 4 GND2 5 MDAT 6 MCLK 7 VDD2 8 U1 ACPL C740 0R R8 GND1 GND1 GND2 P1 RSHUNT P2 RSHUNT 0R R9 0R R10 RUBBER FOOTER RF2 RUBBER FOOTER RF3 RUBBER FOOTER...

Page 11: ...om ACPL C740 EvalKit UG100 11 ACPL C740 Evaluation Kit Board User Guide Isolated Sigma Delta Modulator C740 SDM EVBD PCB Layout Figure 9 C740 SDM EVBD PCB Top Layer Figure 10 C740 SDM EVBD PCB Second...

Page 12: ...Broadcom ACPL C740 EvalKit UG100 12 ACPL C740 Evaluation Kit Board User Guide Isolated Sigma Delta Modulator Figure 11 C740 SDM EVBD PCB Third Layer Figure 12 C740 SDM EVBD PCB Bottom Layer...

Page 13: ...nloading FPGA Code For FPGA configuration via SPI only 1 2 FB2 1 2 FB1 470 R1 0 1 uF C2 GND2 27 R2 GND2 GND2 47 pF C11 GND2 27 R3 1 5K R6 0 47 uF C12 C34 GND2 0 1 uF C3 GND2 0 01 uF C1 GND2 1 2 DNM J1...

Page 14: ...133 GND 61 GND 118 GND 127 U5 XC3S250E GND2 FTDI_D2 FTDI_D3 FTDI_D4 FTDI_D6 FTDI_D7 FTDI_RD USER_IO3 FTDI_WR USER_IO5 FTDI_D1 USER_IO26 USER_IO27 USER_IO28 USER_IO6 USER_IO7 USER_IO8 USER_IO9 USER_IN3...

Page 15: ...Broadcom ACPL C740 EvalKit UG100 15 ACPL C740 Evaluation Kit Board User Guide Isolated Sigma Delta Modulator FPGA EVBD PCB Layout Figure 15 FPGA EVBD PCB Top Layer Figure 16 FPGA EVBD PCB Second Layer...

Page 16: ...Broadcom ACPL C740 EvalKit UG100 16 ACPL C740 Evaluation Kit Board User Guide Isolated Sigma Delta Modulator Figure 17 FPGA EVBD PCB Third Layer Figure 18 FPGA EVBD PCB Bottom Layer...

Page 17: ...ore information please visit www broadcom com Broadcom reserves the right to make changes without further notice to any products or data herein to improve reliability function or design Information fu...

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