1-29
1-133.
Left channel audio from the exciter circuit board is applied to a left channel high
frequency equalizer network in the equalization 1 circuit. The high frequency equalizer
consists integrated circuits U1A, U2, U1B, U3, U4A, and U6A. The equalizer circuit is a
second order state variable low-pass filter designed to compensate for high frequency and
phase problems caused by antenna/phasor units. The filter is equipped with an
adjustable corner frequency. The corner frequency is established by a voltage generated
by potentiometer R20 and buffer U6A. The voltage is applied to
voltage-controlled-amplifiers U2 and U3 which control the corner frequency of the
equalizer circuit. In addition to the variable corner frequency, the filter is equipped with a
variable peak level. Potentiometer R6 controls the signal peak near the corner frequency.
Potentiometer R1 controls the left channel level. The output of the circuit is applied to an
8 microsecond delay circuit.
1-134.
8 MICROSECOND DELAY CIRCUIT.
Integrated circuit U4B is configured as an 8
microsecond delay circuit. The delay circuit is a third order low-pass filter designed to
provide 8 microseconds of delay to match low and mid frequency delay equalization
requirements. The output of the circuit is routed to 8 microsecond delay select jumper
P1A. P1A allows the delay circuit to be bypassed if 8 microseconds of delay is not
required for equalization operation.
1-135.
4 MICROSECOND DELAY CIRCUIT.
Integrated circuit U5A is configured as a 4
microsecond delay circuit. The delay circuit is a third order low-pass filter designed to
provide 4 microseconds of delay to match low and mid frequency delay equalization
requirements. The output of the circuit is routed to 4 microsecond delay select jumper
J1B. J1B allows the delay circuit to be bypassed if 4 microseconds of delay is not required
for equalization operation.
1-136.
ALL-PASS FILTER.
Integrated circuit U5B is configured as an all-pass filter circuit. The
circuit is designed to provide a continuously adjustable 0-6 microsecond delay for
equalization operation. Potentiometer R26 controls the amount of delay.
1-137.
EQUALIZATION SELECTION CIRCUIT.
The outputs of equalization circuits 1 and 2 are
applied to an equalization selection circuit consisting of integrated circuits U23 and U28.
U23 and U28 are single-pole switch arrays designed to select audio from the equalization
1 or equalization 2 circuit. U23 and U28 are controlled by: 1) HIGH equalization 1 and
equalization 2 control signals from latch U44A and 2) a HIGH stereo signal from the
mono/stereo mode decoder circuit. The circuit is designed to select audio in response to
the antenna pattern and mode of operation. For example, stereo audio from equalization
circuit 1 is required. A HIGH from latch U44A will enable the equalization 1 switches in
U23 and U28. U23 and U28 respond by routing audio to an L+R and L-R matrix circuit.
1-138.
L+R AND L-R MATRIX CIRCUIT.
Left and right channel audio from the equalization
selection circuit is applied to an L-R and L+R matrix circuit. The circuit consists of
integrated circuits U24A, U24B, U25A, U26A, U26B, U27A, U29A, U29B, U25B, U31B,
U27B, U27A, and U32. The circuit is designed to generate L+R and L-R audio for
application to a phase modulator circuit.