1-14
1-60.
Comparators U66A/U66B operate in association to monitor high forward power
conditions. U66A/U66B use the high reflected power attack circuitry to reduce the
transmitter power when a high forward power condition occurs. When the transmitter
power is greater than 90%, U66B will output a HIGH. When a high forward power
conditions results in the forward power sample to increase above the voltage reference by
approximately 20%, the output of U66A will go HIGH. The HIGH is applied to AND gate
U47B. With a HIGH from U66B, U47B will output a HIGH to OR gate U62A. U62A will
output a HIGH to AND gate U47A. With a HIGH enable failure signal, U47A will output:
1) a HIGH reflected power high attack signal to priority encoder U28 and 2) a HIGH to
latch U67A. The HIGH reflected power attack signal is used by U28 to initiate an attack
sequence to reduce the transmitter output power. The HIGH to U67A will configure
U67A to output a HIGH reflected power signal to enable latch U48D. U48D will output a
HIGH to bias: 1) alarm status indicator driver transistors Q34 and Q35 on and 2) antenna
indicator driver Q28 on. When the transmitter power is reduced to approximately 90%,
the output of U66B will go LOW. The LOW is applied to U47B. U47B will output a LOW
through U62A to U47A. U47A will respond by routing a LOW to terminate the high
reflected power attack signal. The indicators will remain illuminated until the alarm
reset switch is depressed.
1-61.
High Reflected Power Circuitry.
Integrated circuit U65C monitors reflected power
conditions. U65C compares a reflected power sample from U64C to a voltage reference.
When the reflected power sample increases above the voltage reference, the output of
U65C will go HIGH. The HIGH is applied through OR gate U62A to AND gate U47A.
With a HIGH enable failure signal, U47A will output: 1) a HIGH reflected power high
attack signal to priority encoder U28 and 2) a HIGH to latch U67A. The HIGH reflected
power attack signal is used by U28 to initiate an attack sequence to reduce the
transmitter output power. The HIGH to U67A will configure U67A to output a HIGH
reflected power signal to enable latch U48D. U48D will output a to HIGH to bias:
1) alarm status indicator driver transistors Q34 and Q35 on and 2) antenna mismatch
indicator driver Q28 on.
1-62.
Over-temperature Circuitry.
Over-temperature conditions are monitored by an
over-temperature fault detection circuit. A dc voltage representing the transmitter
temperature is applied to: 1) integrated circuits U65A/U65B and 2) integrated circuit
U61A. When the temperature voltage increase above a reference voltage, the output of
U65A will go HIGH. The HIGH is routed to AND gate U51D. With a HIGH enable
failure signal, U51D will output: 1) a HIGH over-temperature attack signal to priority
encoder U28 and 2) a HIGH to latch U67C. The HIGH over temperature attack signal is
used by U28 to initiate an attack sequence to reduce the transmitter output power. The
HIGH to U67C will configure U67C to output a HIGH: 1) over-temperature signal to
latch U49B and 2) to AND gate U47D. The output of U49B will go HIGH to bias: 1) alarm
status indicator driver transistors Q34 and Q35 on and 2) over-temperature indicator
drivers Q32 and Q36 on. When the transmitter temperature is reduced to 70 degrees C,
the output of U65A will go LOW and the output of U65B will go HIGH. The LOW is
applied to U51D. U51D will output a LOW to terminate the over-temperature attack
signal. The indicators will remain illuminated until the alarm reset switch is depressed.
The from HIGH from U65B is also applied to U47D. With the HIGH from U67C, U47D
will output a over temperature release signal to encoder U28.
1-63.
U61A is configured as a comparator designed to monitor extreme temperature conditions.
When the temperature voltage increases above the reference voltage, the output of U61A
will go HIGH. U61A will output a HIGH temperature shutdown command to U13A of the
transmitter off control circuit.