BL602/604 Reference Manual
• ADC CH7
• ADC CH8
• ADC CH9
• ADC CH10
• ADC CH11
• DAC OUTA
• DAC OUTB
• VBAT/2
• TSEN
• VREF
• GND
It should be noted that if VBAT/2 or TSEN is selected as the input signal to be acquired, gpadc_vbat_en or gpadc_-
ts_en needs to be set.
The ADC module can support single-ended input or differential input. If it is single-ended input mode, the negative
input channel needs to select GND.
4.3.3 ADC clock
The working clock source of the ADC module is shown in the following figure:
Divider
96M
PLL
XCLK
ADC
gpadc_clk_div_ra o
gpadc_32m_clk_sel
ADC
functional module
Figure 4.2: ADC Clock
The ADC clock source can select 96M, XTAL or internal RC32M from the PLL. The clock source selection is set in
the GLB module. At the same time, the GLB module also provides the clock frequency division. By default, the ADC
clock source is 96M. The frequency is 2, and the clock to the ADC module is 32M.
Inside the ADC module, a clock frequency division is provided. The default is 16 frequency division, so the internal
BL602/604 Reference Manual
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