Bouffalo Lab BL602, Reference Manual, Page: 118 / 195

BL602/604 Reference Manual
is greater than its set threshold, a DMA request will be initiated , DMA will move data to TX FIFO or out of RX FIFO
according to the setting.
9.3.8 SPI interrupt
SPI has a variety of interrupt control, including the following interrupt modes:
• SPI transfer end interrupt
• TX FIFO request interrupt
• RX FIFO request interrupt
• Slave mode transfer timeout interrupt
• Slave mode TX overload interrupt
• TX / RX FIFO overflow interrupt
In master mode, the SPI transfer end interrupt is triggered at the end of each frame of data transfer; in slave mode,
the SPI transfer end interrupt is triggered when the CS signal is released. The TX / RX FIFO request interrupt will
be triggered when its available FIFO count is greater than its set threshold. When the condition is not met, the
interrupt flag will be automatically cleared. Slave mode transmission timeout interrupt is triggered when the threshold
is exceeded in slave mode and no clock signal is received. If the TX / RX FIFO overflows or underflows, the TX / RX
FIFO overflow interrupt will be triggered. When the FIFO clear bit TFC / RFC is set to 1, the corresponding FIFO will
be cleared and the overflow interrupt flag will be automatically cleared.
Query the interrupt status through register SPI_INT_STS and write 1 to the corresponding bit to clear the interrupt.
9.4 Register description
Name
Description
spi_config SPI configuration register
spi_int_sts SPI interrupt status
spi_bus_busy SPI bus busy
spi_prd_0 SPI length control register
spi_prd_1 SPI length of interval
spi_rxd_ignr SPI ingnore function
spi_sto_value SPI time-out value
spi_fifo_config_0 SPI FIFO configuration register0
spi_fifo_config_1 SPI FIFO configuration register1
spi_fifo_wdata SPI FIFO write data
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