BL602/604 Reference Manual
10.3 Function description
10.3.1 Data format description
Normal UART communication data is composed of a start bit, a data bit, a parity bit, and a stop bit. The BL602’s UART
supports configurable data bits, parity bits, and stop bits, all of which are set in the UTX_CONFIG and URX_CONFIG
registers. The waveform of one frame of data is shown below:
8bit Single data Odd parity
bit 0
bit 1
bit 2
Start
Start
odd
Stop
bit 7
bit 6
bit 5
bit 4
bit 3
Figure 10.1: UART data
The start bit of a data frame occupies 1-bit, and the stop bit can be configured to be 0.5 / 1 / 1.5 / 2 bits wide by
configuring <CR_UTX_BIT_CNT_P> and <CR_URX_BIT_CNT_P>. The start bit is low and the stop bit is high.
The data bit width can be configured to 5/6/7/8 bit width by <CR_UTX_BIT_CNT_D> and <CR_URX_BIT_CNT_D>.
When <CR_UTX_PRT_EN> and <CR_URX_PRT_EN> are set, the data frame adds a parity bit after the data. <CR_-
UTX_PRT_SEL> and <CR_URX_PRT_SEL> are used to select odd or even parity. When the receiver detects a parity
error in the input data, a parity error interrupt is generated.
Odd parity calculation method: If the current data bit 1 is an odd number, the odd parity bit is 0; otherwise, it is 1.
Calculation method of even parity: If the number of current data bit 1 is odd, even parity is 1; otherwise it is 0.
10.3.2 Basic architecture diagram
10.3.3 Clock source
The UART has two clock sources: 160MHz APB_CLK and FCLK. The frequency divider in the clock is used to divide
the clock source and then generate a clock signal to drive the UART module. As shown below:
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