manualshive.com logo in svg

Bouffalo Lab BL602, Reference Manual, Page: 14 / 195

Share
Download
Bouffalo Lab BL602 Reference Manual Download Page 14

BL602/604 Reference Manual

11.3 Master tx and slave rx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

144

11.4 Master rx and slave tx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

144

11.5 Tx and Rx together . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

145

12.1 Pwm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

158

13.1 Timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

174

13.2 Watchdog timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

175

13.3 Timer Preload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

176

13.4 Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

177

13.5 Watchdog alarm mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

178

BL602/604 Reference Manual

14/ 195

@2020 Bouffalo Lab

Summary of Contents for BL602

Page 1: ...BL602 604 Reference Manual version 1 2 copyright 2020 www bouffalolab com...

Page 2: ...11 2 2 Reset source 11 2 3 Clock source 12 3 GLB 14 3 1 Introduction 14 3 2 GLB function description 14 3 2 1 Clock 14 3 2 2 Reset 14 3 2 3 Bus 14 3 2 4 Memory 15 3 2 5 GPIO overview 15 3 2 6 GPIO ma...

Page 3: ...7 3 3 11 GPIO_CFGCTL6 28 3 3 12 GPIO_CFGCTL7 28 3 3 13 GPIO_CFGCTL8 29 3 3 14 GPIO_CFGCTL9 30 3 3 15 GPIO_CFGCTL10 31 3 3 16 GPIO_CFGCTL11 32 3 3 17 GPIO_CFGCTL12 33 3 3 18 GPIO_CFGCTL13 33 3 3 19 GPI...

Page 4: ...c_reg_scn_neg2 54 4 4 10 gpadc_reg_status 54 4 4 11 gpadc_reg_isr 55 4 4 12 gpadc_reg_result 55 4 4 13 gpadc_reg_raw_result 56 4 4 14 gpadc_reg_define 56 5 DAC 57 5 1 Introduction 57 5 2 Main features...

Page 5: ...6 DMA_RawIntTCStatus 70 6 5 7 DMA_RawIntErrorStatus 71 6 5 8 DMA_EnbldChns 71 6 5 9 DMA_SoftBReq 71 6 5 10 DMA_SoftSReq 72 6 5 11 DMA_SoftLBReq 72 6 5 12 DMA_SoftLSReq 72 6 5 13 DMA_Config 73 6 5 14...

Page 6: ...sources 87 7 3 2 Cache 87 7 4 Register description 88 7 4 1 l1c_config 89 7 4 2 hit_cnt_lsb 89 7 4 3 hit_cnt_msb 89 7 4 4 miss_cnt 90 8 IR 91 8 1 Introduction 91 8 2 IR main features 91 8 3 Function d...

Page 7: ...a_count 103 8 4 19 irrx_data_word0 104 8 4 20 irrx_data_word1 104 8 4 21 irrx_swm_fifo_config_0 104 8 4 22 irrx_swm_fifo_rdata 105 9 SPI 106 9 1 Introduction 106 9 2 Main features 106 9 3 Function des...

Page 8: ...a format description 118 10 3 2 Basic architecture diagram 118 10 3 3 Clock source 118 10 3 4 Baud rate setting 119 10 3 5 Transmitter 120 10 3 6 receiver 120 10 3 7 Automatic baud rate detection 121...

Page 9: ...ions 134 11 3 2 Data transmission format 134 11 3 3 Arbitration 135 11 4 I2C clock setting 136 11 5 I2C configuration process 136 11 5 1 Configuration item 136 11 5 2 Read and write flags 137 11 5 3 S...

Page 10: ...ion description 148 12 3 1 Clock and divider 148 12 3 2 Pulse generation principle 149 12 3 3 PWM interrupt 150 12 4 Register description 150 12 4 1 pwm_int_config 151 12 4 2 pwm0_clkdiv 152 12 4 3 pw...

Page 11: ...e2 162 12 4 29 pwm4_period 163 12 4 30 pwm4_config 163 12 4 31 pwm4_interrupt 164 13 TIMER 165 13 1 Introduction 165 13 2 Main features 166 13 3 Function description 166 13 3 1 8 bit divider 166 13 3...

Page 12: ...3 4 18 WMER 177 13 4 19 WMR 178 13 4 20 WVR 178 13 4 21 WSR 179 13 4 22 TICR2 179 13 4 23 TICR3 180 13 4 24 WICR 180 13 4 25 TCER 180 13 4 26 TCMR 181 13 4 27 TILR2 181 13 4 28 TILR3 182 13 4 29 WCR 1...

Page 13: ...1c architecture 95 7 2 Cache architecture 97 8 1 nec logical 101 8 2 nec 101 8 3 rc5 logical 101 8 4 rc5 102 9 1 SPI clock 116 9 2 SPI ignore 117 10 1 UART data 127 10 2 UART clock 128 10 3 UART sampl...

Page 14: ...ster rx and slave tx 144 11 5 Tx and Rx together 145 12 1 Pwm 158 13 1 Timer block diagram 174 13 2 Watchdog timer block diagram 175 13 3 Timer Preload 176 13 4 Watchdog timing 177 13 5 Watchdog alarm...

Page 15: ...upt distribution 19 3 1 Pin description 26 3 1 Pin description 27 4 1 ADC internal signals 47 4 2 ADC external pins 47 4 3 Meaning of ADC conversion result 50 7 1 WayDisable settings 96 11 1 Pin lists...

Page 16: ...cache and system shared memory Off chip memory supports Flash expansion 1 2 Main features RISC V 32 bit with floating point Multi layer 32 bit AHB bus architecture 96KB high speed memory 180KB system...

Page 17: ...mory RETRAM 0x40010000 4KB Deep sleep memory RAM reserved HBN 0x4000F000 4KB Deep Sleep Control Hibernation PDS 0x4000E000 4KB Sleep control power down sleep SDU 0x4000D000 4KB SDIO control DMA 0x4000...

Page 18: ...use address 0x22008000 for access ROM 0x21000000 128KB Read only memory 1 4 Interrupt source BL602 BL604 contains a total of 18 interrupt sources The interrupt sources and corresponding interrupt num...

Page 19: ...rupt TIMER_WDT IRQ_NUM_BASE 38 Watch Dog Interrupt GPIO GPIO_INT0 IRQ_NUM_BASE 44 GPIO Interrupt PDS PDS_WAKEUP IRQ_NUM_BASE 50 PDS Wakeup Interrupt HBN HBN_OUT0 IRQ_NUM_BASE 51 Hibernate out 0 Interr...

Page 20: ...atchdog reset When the watchdog alarm triggers a reset signal the reset management unit will reset the chip system after necessary preparations and the internal logic of the watchdog will record the s...

Page 21: ...equency can be selected from 24 32 38 4 40MHz XTAL32K External crystal clock frequency 32kHz RC32K RC oscillator clock 32kHz provides calibration RC32M RC oscillator clock frequency 32MHz provides cal...

Page 22: ...Hz 1 1 CG pwm clk 0 RC32K XTAL32K DIV CG en 11bit f32k_sel RC32M clkpll_xtal_rc32m_sel PLL xtal_clk root_clk_sel 0 pll_en bclk_en bclk_div hclk_en hclk_div root_clk_sel 1 pll_sel sel sel sel sel 3bit...

Page 23: ...o the relevant chapter of the system clock 3 2 2 Reset Provide individual reset function for each peripheral and chip reset function The chip reset includes CPU reset just reset the CPU module the pro...

Page 24: ...es pull up pull down and floating In addition GPIO also provides interrupt functions which can be configured as rising edge trigger falling edge trigger or High low level trigger 3 2 6 GPIO main featu...

Page 25: ...te interrupt detection and control interrupt inout Rd Ru GND VCC bus read peripheral optional function output Figure 3 1 GPIO Basic Struct 3 2 8 GPIO function The function of GPIO is set through the G...

Page 26: ...ion GPIO SDIO FLASH SPI I2C UART PWM Analog SWGPIO JTAG GPIO0 CLK D1 MISO SCL SIG0 CH0 SWGPIO0 TMS GPIO1 CMD D2 MOSI SDA SIG1 CH1 SWGPIO1 TDI GPIO2 DAT0 D2 SS SCL SIG2 CH2 SWGPIO2 TCK GPIO3 DAT1 D3 SC...

Page 27: ..._SEL include 0 UART0_RTS 1 UART0_CTS 2 UART0_TXD 3 UART0_RXD 4 UART1_RTS 5 UART1_CTS 6 UART1_TXD 7 UART1_RXD Take GPIO0 as an example when fun_sel selects UART GPIO0 selects UART_SIG0 By default the v...

Page 28: ...led by the peripheral At this time The input signal is the output signal but it will not be collected by the output peripheral When the peripheral needs both input and output the input and output can...

Page 29: ...configuration GPIO_CFGCTL10 GPIO20 GPIO21 configuration GPIO_CFGCTL11 GPIO22 GPIO23 configuration GPIO_CFGCTL12 GPIO24 GPIO25 configuration GPIO_CFGCTL13 GPIO26 GPIO27 configuration GPIO_CFGCTL14 GPI...

Page 30: ...UART EN RSVD UARTDIV Bits Name Type Reset Description 31 24 DMAEN R W 8 hff CH0 1 2 AHBm AHBs Rqs 23 14 RSVD 13 12 SFSEL R W 2 d2 Flash Clock Select 0 120M 1 80M 2 HCLK 3 96M 11 SFEN R W 1 Flash Cloc...

Page 31: ...Enable Default Enable 7 5 RSVD 4 0 SPIDIV R W 5 d3 SPI Clock Divider BUS_CLK N 1 default BUS_CLK 4 3 3 4 GPADC_32M_SRC_CTRL Address 0x400000a4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD 15...

Page 32: ...t Default SDIO 23 22 RSVD 21 GP1PD R W 0 GPIO Pull Down Control 20 GP1PU R W 0 GPIO Pull Up Control 19 18 GP1DRV R W 0 GPIO Driving Control 17 GP1SMT R W 1 GPIO SMT Control 16 GP1IE R W 1 GPIO Input E...

Page 33: ...0 GPIO Driving Control 17 GP3SMT R W 1 GPIO SMT Control 16 GP3IE R W 1 GPIO Input Enable 15 12 RSVD 11 8 GP2FUNC R W 4 h1 GPIO Function Select Default SDIO 7 6 RSVD 5 GP2PD R W 0 GPIO Pull Down Contr...

Page 34: ...own Control 4 GP4PU R W 0 GPIO Pull Up Control 3 2 GP4DRV R W 0 GPIO Driving Control 1 GP4SMT R W 1 GPIO SMT Control 0 GP4IE R W 1 GPIO Input Enable 3 3 8 GPIO_CFGCTL3 Address 0x4000010c 31 30 29 28 2...

Page 35: ...CTL4 Address 0x40000110 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD GP9FUNC RSVD GP9 PD GP9 PU GP9DRV GP9 SMT GP9 IE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD GP8FUNC RSVD GP8 PD GP8 PU GP8D...

Page 36: ...D GP10FUNC RSVD GP10 PD GP10 PU GP10DRV GP10 SMT GP10 IE Bits Name Type Reset Description 31 28 RSVD 27 24 GP11FUNC R W 4 hE GPIO Function Select Default JTAG 23 22 RSVD 21 GP11PD R W 0 GPIO Pull Down...

Page 37: ...FUNC R W 4 hB GPIO Function Select Default SWGPIO 23 22 RSVD 21 GP13PD R W 0 GPIO Pull Down Control 20 GP13PU R W 0 GPIO Pull Up Control 19 18 GP13DRV R W 0 GPIO Driving Control 17 GP13SMT R W 1 GPIO...

Page 38: ...GPIO Driving Control 17 GP15SMT R W 1 GPIO SMT Control 16 GP15IE R W 1 GPIO Input Enable 15 12 RSVD 11 8 GP14FUNC R W 4 hE GPIO Function Select Default JTAG 7 6 RSVD 5 GP14PD R W 0 GPIO Pull Down Con...

Page 39: ...ontrol 4 GP16PU R W 0 GPIO Pull Up Control 3 2 GP16DRV R W 0 GPIO Driving Control 1 GP16SMT R W 1 GPIO SMT Control 0 GP16IE R W 1 GPIO Input Enable 3 3 14 GPIO_CFGCTL9 Address 0x40000124 31 30 29 28 2...

Page 40: ...Address 0x40000128 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD GP21FUNC RSVD GP21 PD GP21 PU GP21DRV GP21 SMT GP21 IE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD GP20FUNC RSVD GP20 PD GP20 PU...

Page 41: ...SVD GP22FUNC RSVD GP22 PD GP22 PU GP22DRV GP22 SMT GP22 IE Bits Name Type Reset Description 31 28 RSVD 27 24 GP23FUNC R W 4 hB GPIO Function Select Default SWGPIO 23 22 RSVD 21 GP23PD R W 0 GPIO Pull...

Page 42: ...UNC R W 4 hB GPIO Function Select Default SWGPIO 23 22 RSVD 21 GP25PD R W 0 GPIO Pull Down Control 20 GP25PU R W 0 GPIO Pull Up Control 19 18 GP25DRV R W 0 GPIO Driving Control 17 GP25SMT R W 1 GPIO S...

Page 43: ...ll Up Control 19 18 GP27DRV R W 0 GPIO Driving Control 17 GP27SMT R W 1 GPIO SMT Control 16 GP27IE R W 1 GPIO Input Enable 15 12 RSVD 11 8 GP26FUNC R W 4 hB GPIO Function Select Default SWGPIO 7 6 RSV...

Page 44: ...scription 31 6 RSVD 5 GP28PD R W 0 GPIO Pull Down Control 4 GP28PU R W 0 GPIO Pull Up Control 3 2 GP28DRV R W 0 GPIO Driving Control 1 GP28SMT R W 1 GPIO SMT Control 0 GP28IE R W 1 GPIO Input Enable B...

Page 45: ...sed to measure the supply voltage In addition the ADC can also be used for temperature detection by measuring the internal external diode voltage 4 2 ADC main features High performance 12 bit 14 bit o...

Page 46: ...el selector program controlled amplifier ADC sampling module data processing module and FIFO The input channel selector is used to select the channel to be sampled It contains both external analog sig...

Page 47: ...AC module output DACOUTB Input DAC module output Table 4 2 ADC external pins External pins Signal type Description VDDA Input Analog power supply and positive reference voltage for the ADC VSSA Input...

Page 48: ...source of the ADC module is shown in the following figure Divider 96M PLL XCLK ADC gpadc_clk_div_ra o gpadc_32m_clk_sel ADC functional module Figure 4 2 ADC Clock The ADC clock source can select 96M X...

Page 49: ...c_conv_start control bit to start the conversion In scan conversion mode the gpadc_cont_conv_en control bit needs to be set to 1 and the number of conversion channels set by the ADC according to the g...

Page 50: ...s OSR 256 The ADC conversion result is left justified When 12 bits are selected bit15 bit4 of the conversion result is valid When 14 bits are selected bit15 bit2 of the conversion result is valid Whe...

Page 51: ...number of FIFO data according to gpadc_fifo_data_count and read these data from the FIFO Interrupt mode The CPU sets gpadc_rdy_mask to 0 and the ADC will generate an interrupt when there is data in t...

Page 52: ...o start conversion When the conversion is complete and needs to be converted again gpadc_conv_start needs to be set to 0 and then set to 1 in order to trigger the conversion again 4 3 9 VBAT measureme...

Page 53: ...n If the internal diode is selected gpadc_tsext_sel 0 External diode gpadc_tsext_sel 1 select the forward input channel according to the actual situation If it is an internal diode select the TSEN cha...

Page 54: ...ription 31 24 RSVD 23 22 FIFOTHL R W 2 d0 fifo threshold 2 b00 1 data 2 b01 4 data 2 b10 8 data 2 b11 16 data 21 16 FIFODACN R 6 d0 fifo data number 15 RSVD 14 FURM R W 1 b0 write 1 mask 13 FORM R W 1...

Page 55: ...A R 26 d0 GPADC finial conversion result stored in the FIFO 4 4 3 gpadc_reg_cmd Address 0x4000f90c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD STEN SENSEL CSPU RSVD MBEN MPG M1D M2D DWEN RSVD...

Page 56: ...nable 1 b0 single 1 b1 diff 19 M2D R W 1 b0 mic2 diff enable 1 b0 single 1 b1 diff 18 DWEN R W 1 b0 dwa enable 1 b0 dwa disable 1 b1 dwa enable 17 RSVD 16 BMB R W 1 b0 micboost amp bypass 1 b0 not byp...

Page 57: ...2 5 h23 31 avss 7 3 NEGSEL R W 5 hf select adc negative input in none scan mode 5 h0 gpip_ch 0 5 h1 gpip_ch 1 5 h2 gpip_ch 2 5 h3 gpip_ch 3 5 h4 gpip_ch 4 5 h5 gpip_ch 5 5 h6 gpip_ch 6 5 h7 gpip_ch 7...

Page 58: ...8 7 6 5 4 3 2 1 0 RSVD RSSEL CTCV OCEN Bits Name Type Reset Description 31 RSVD 30 29 V18SEL R W 2 h0 internal vdd18 select 28 27 V11SEL R W 2 h0 internal vdd11 select 26 DTEN R W 1 h0 Dither compens...

Page 59: ...gpadc_scan_ neg_5 4 b0110 select gpadc_scan_pos_6 and gpadc_scan_ neg_6 4 b0111 select gpadc_scan_pos_7 and gpadc_scan_ neg_7 4 b1000 select gpadc_scan_pos_8 and gpadc_scan_ neg_8 4 b1001 select gpadc...

Page 60: ...Address 0x4000f914 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TDCR DLYSEL PGA1GAIN PGA2GAIN TESTSEL ATEN BSEL CM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CM PCEN PEN POCAL PVCM TSEN DDM VBEN VRFS DI...

Page 61: ...R W 2 h2 Audio PGA output common mode control 2 b00 cm 1V 2 b11 cm 1 2V 2 b11 cm 1 4V 2 b11 cm 1 6V 6 TSEN R W 1 b0 1 h0 disable temperature sensor 1 h1 enable tempera ture sensor 5 DDM R W 1 b0 1 h0...

Page 62: ...SCANP11 SCANP10 SCAN9 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SCAN9 SCANP8 SCANP7 SCANP6 Bits Name Type Reset Description 31 30 RSVD 29 25 SCANP11 R W 5 hf definition is the same as adc_reg_cmd adc_pos...

Page 63: ...20 19 18 17 16 RSVD SCANN11 SCANN10 SCAN9 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SCAN9 SCANN8 SCANN7 SCANN6 Bits Name Type Reset Description 31 30 RSVD 29 25 SCANN11 R W 5 hf definition is the same as...

Page 64: ...RSVD 9 PSM R W 1 h0 write 1 mask 8 NSM R W 1 h0 write 1 mask 7 6 RSVD 5 PSC R W 1 b0 Write 1 to clear flag 4 NSC R W 1 b0 Write 1 to clear flag 3 2 RSVD 1 PS R 1 b0 ADC data positive side saturation...

Page 65: ...7 16 RSVD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD RAWDATA Bits Name Type Reset Description 31 12 RSVD 11 0 RAWDATA R 12 h0 ADC Raw data 4 4 14 gpadc_reg_define Address 0x4000f938 31 30 29 28 27 26...

Page 66: ...features DAC modulation accuracy is 10 bits DAC input clock can be selected as 32k 16k 8k or 512k Support DMA to transfer memory to DAC modulation register Support dual channel playback DMA transport...

Page 67: ...h of 32 bit in which the high 16 bits will be modulated on the pins of ChannelA and the low 16 bits will be modulated on the pins of ChannelB 5 4 Register description Name Description gpdac_config GPD...

Page 68: ...5 A Inverse of channel A 19 16 CHASEL R W 0 Channel A Source Select 0 Reg 1 DMA 2 DMA Filter 3 Sin Gen 15 11 RSVD 10 8 MODE R W 0 0 32k 1 16k 3 8k 4 512k for DMA only 7 6 RSVD 5 4 DSMMODE R W 0 0 bypa...

Page 69: ...A2 A5 A4 Note 20 h0 11 0 or 4 h0 27 16 4 h0 11 0 3 1 RSVD 0 DMATXEN R W 0 GPDAC DMA TX enable 5 4 3 gpdac_dma_wdata Address 0x40002048 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DMAWDA 15 14 13 1...

Page 70: ...ission data size data source address and destination address 6 2 DMA main features 4 independently configurable channels requests on DMA Independent control of source and destination access width sing...

Page 71: ...CPU The peripheral device makes a bus request to the CPU to take over the bus control right through the DMA After the CPU receives the signal after the current bus cycle ends it will respond to the D...

Page 72: ...0 REQ1 REQ31 Figure 6 1 DMA architecture The DMA includes a set of AHB Master interfaces and a set of AHB Slave interfaces The AHB Master interface actively accesses memory or peripherals through the...

Page 73: ...upport The SrcPeripheral source and DstPeripheral destination are configured to determine the peripherals that the current DMA cooperates with The relationship is 0 3 UART 6 7 I2C 10 11 SPI 22 23 ADC...

Page 74: ...After completing the data transfer of the current linked list read the DMA_C0LLI register to obtain the start address of the next linked list and directly transfer the data in the next linked list En...

Page 75: ...s to 1 to enable the automatic address accumulation mode the DTW and STW bits set the transmission width of the source and destination and the DBS and SBS bits set the burst type of the source and des...

Page 76: ...MA_C0SrcAddr to the source peripheral address 2 Set the value of the register DMA_C0DstAddr to the target memory address 3 Select the transfer mode and set the value of the DMA_C0Config FLOWCTRL bit t...

Page 77: ...el DMA source address DMA_C1DstAddr Channel DMA Destination address DMA_C1LLI Channel DMA link list DMA_C1Control Channel DMA bus control DMA_C1Config Channel DMA configuration DMA_C2SrcAddr Channel D...

Page 78: ...29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD INTTCSTA Bits Name Type Reset Description 31 8 RSVD 7 0 INTTCSTA R 0 Interrupt terminal count request status...

Page 79: ...30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD IEC Bits Name Type Reset Description 31 8 RSVD 7 0 IEC W 0 Interrupt error clear 6 5 6 DMA_RawIntTCStatus A...

Page 80: ...SOTEIPTM R 0 Status of the error interrupt prior to masking 6 5 8 DMA_EnbldChns Address 0x4000c01c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD CES B...

Page 81: ...Description 31 0 SSR R W 0 Software single request 6 5 11 DMA_SoftLBReq Address 0x4000c028 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SLBR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SLBR Bits Name Typ...

Page 82: ...scription 31 2 RSVD 1 AHBMEC R W 0 AHB Master endianness configuration 0 little endian 1 big endian 0 SDMAEN R W 0 SMDMA Enable 6 5 14 DMA_Sync Address 0x4000c034 31 30 29 28 27 26 25 24 23 22 21 20 1...

Page 83: ...22 21 20 19 18 17 16 DMADA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DMADA Bits Name Type Reset Description 31 0 DMADA R W 0 DMA Destination address 6 5 17 DMA_C0LLI Address 0x4000c108 31 30 29 28 27 26...

Page 84: ...VD 24 IMTMMODE R W 0 In Memory to memory mode Set this bit high when Src data size is larger than Dst 23 21 DTW R W 3 b010 Destination transfer width 8 16 32 20 18 STW R W 3 b010 Source transfer width...

Page 85: ...o peripheral DMA 010 Peripheral to memory DMA 011 Source peripheral to Destination peripheral DMA 100 Source peripheral to Destination peripheral Destina tion peripheral 101 Memory to peripheral perip...

Page 86: ...Destination address 6 5 22 DMA_C1LLI Address 0x4000c208 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LLI 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LLI RSVD Bits Name Type Reset Description 31 2 LLI R...

Page 87: ...tination burst size 1 4 8 16 14 12 SBSIZE R W 3 b001 Source burst size 1 4 8 16 Note CH FIFO Size is 16Bytes and SBSize Swidth should 16B 11 0 TRANSIZE R W 0 Transfer size 0 4095 Number of data transf...

Page 88: ...mory peripheral 111 Source peripheral to Destination peripheral Source peripheral 10 6 DSTPH R W 0 Destination peripheral 23 22 GPADC 21 18 I2S 17 14 PDM 13 10 SPI 9 6 I2C 5 0 UART 5 1 SRCPH R W 0 Sou...

Page 89: ...irst linked list item Bits 1 0 must be 0 1 0 RSVD 6 5 28 DMA_C2Control Address 0x4000c30c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 I PROT DI SI RSVD DWIDTH SWIDTH DBSIZE 15 14 13 12 11 10 9 8 7...

Page 90: ...16B 11 0 TRANSIZE R W 0 Transfer size 0 4095 Number of data transfers left to complete when the SMDMA is the flow controller 6 5 29 DMA_C2Config Address 0x4000c310 31 30 29 28 27 26 25 24 23 22 21 20...

Page 91: ...mory peripheral 111 Source peripheral to Destination peripheral Source peripheral 10 6 DSTPH R W 0 Destination peripheral 23 22 GPADC 21 18 I2S 17 14 PDM 13 10 SPI 9 6 I2C 5 0 UART 5 1 SRCPH R W 0 Sou...

Page 92: ...irst linked list item Bits 1 0 must be 0 1 0 RSVD 6 5 33 DMA_C3Control Address 0x4000c40c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 I PROT DI SI RSVD DWIDTH SWIDTH DBSIZE 15 14 13 12 11 10 9 8 7...

Page 93: ...16B 11 0 TRANSIZE R W 0 Transfer size 0 4095 Number of data transfers left to complete when the SMDMA is the flow controller 6 5 34 DMA_C3Config Address 0x4000c410 31 30 29 28 27 26 25 24 23 22 21 20...

Page 94: ...0 Source peripheral to Destination peripheral Destina tion peripheral 101 Memory to peripheral peripheral 110 Peripheral to memory peripheral 111 Source peripheral to Destination peripheral Source per...

Page 95: ...Cache Control 8KB 8KB 8KB 8KB way0 way1 way2 way3 L1C Figure 7 1 L1c architecture L1C is a high speed unit integrated between the processor and Flash Because the speed of the processor is very fast wh...

Page 96: ...djust the memory usage method and efficiency according to the actual situation The default size of the cache is 32K divided into 4 ways each way is 8K the unit of adjustment is 1 way which is 8K The d...

Page 97: ...e address comparison is successful the representative can directly get data from the cache Conversely the cache processor will capture related data through the AHB Master and put the data into the cac...

Page 98: ...7 2 RSVD 1 CNTEN R W 0 Cache performance counter enable 0 CACABLE R W 0 Cachable region enable 7 4 2 hit_cnt_lsb Address 0x40009004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CNTLSB 15 14 13 12...

Page 99: ...count hit_cnt_msb 23 2 hit_cnt_lsb 7 4 4 miss_cnt Address 0x4000900c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MISSCNT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MISSCNT Bits Name Type Reset Descript...

Page 100: ...r into the corresponding electrical signal and send it to the rear amplifier 8 2 IR main features Receiving data with NEC RC 5 protocol Receiving arbitrary format data in pulse width counting mode Pow...

Page 101: ...0 0 0 0 1 0 1 1 0 0 0 0 Figure 8 2 nec The first pulse is a high level pulse of 9ms and a low level of 4 5ms followed by an 8 bit address code and its inverse code and then an 8 bit command code and i...

Page 102: ...in turn using its clock and then store the data in a 64 byte depth receiving FIFO 8 3 3 Normal sending mode Users can configure the corresponding configurations of the head pulse tail pulse logic 0 a...

Page 103: ...errupt by register IRRX_INT_STS 8 4 Register description Name Description irtx_config IR TX configuration register irtx_int_sts IR TX interrupt status irtx_data_word0 IR TX data word0 irtx_data_word1...

Page 104: ...0 is Low Idle phase 1 is High Active L H 10 TXTPEN R W 1 b1 Enable signal of tail pulse Don t care if SWM is enabled 9 TXHHLI R W 1 b0 Tail pulse H L inverse signal Don t care if SWM is enabled 0 Pha...

Page 105: ...ted after finish 8 4 2 irtx_int_sts Address 0x4000a604 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD TXE EN RSVD TXE CLR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD TXE MASK RSVD TXE INT Bits Na...

Page 106: ...3 12 11 10 9 8 7 6 5 4 3 2 1 0 TXDW1 Bits Name Type Reset Description 31 0 TXDW1 R W 32 h0 TX data word 1 Don t care if SWM is enabled 8 4 5 irtx_pulse_width Address 0x4000a610 31 30 29 28 27 26 25 24...

Page 107: ...head pulse phase 1 Don t care if SWM is enabled 19 16 TXHPH0W R W 4 d15 Pulse width of head pulse phase 0 Don t care if SWM is enabled 15 12 TXL1PH1W R W 4 d2 Pulse width of logic1 phase 1 Don t care...

Page 108: ...Reset Description 31 0 TXSWPW1 R W 32 h0 IRTX Software Mode pulse width data 8 15 each pulse is represented by 4 bit 3 0 is the 1st pulse 7 4 is the 2nd pulse 11 8 is the 3rd pulse etc 8 4 9 irtx_swm...

Page 109: ...e 3rd pulse etc 8 4 11 irtx_swm_pw_4 Address 0x4000a650 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TXSWPW4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXSWPW4 Bits Name Type Reset Description 31 0 TXSW...

Page 110: ...e Reset Description 31 0 TXSWPW6 R W 32 h0 IRTX Software Mode pulse width data 48 55 each pulse is represented by 4 bit 3 0 is the 1st pulse 7 4 is the 2nd pulse 11 8 is the 3rd pulse etc 8 4 14 irtx_...

Page 111: ...MODE R W 2 d0 IRRX mode 0 NEC 1 RC5 2 SW pulse width detection mode SWM 3 Reserved 1 RXININV R W 1 b1 Input inverse signal 0 RXEN R W 1 b0 Enable signal of IRRX function Asserting this bit will trigge...

Page 112: ...11 10 9 8 7 6 5 4 3 2 1 0 RXDATH Bits Name Type Reset Description 31 16 RXETH R W 16 d8999 Pulse width threshold to trigger END condition 15 0 RXDATH R W 16 d3399 Pulse width threshold for Logic0 1 de...

Page 113: ...17 16 RXDAW1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXDAW1 Bits Name Type Reset Description 31 0 RXDAW1 R 32 h0 RX data word 1 8 4 21 irrx_swm_fifo_config_0 Address 0x4000a6c0 31 30 29 28 27 26 25 24...

Page 114: ...RXFCLR W1C 1 b0 Clear signal of RX FIFO 8 4 22 irrx_swm_fifo_rdata Address 0x4000a6c4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXFRDA Bits Name Type...

Page 115: ...els each have a FIFO with a depth of 4 words Both master and slave devices support 4 clock formats CPOL CPHA Both master and slave devices support 1 2 3 4 byte transmission mode Flexible clock configu...

Page 116: ...Polarity 1 Clock Phase 1 Clock Polarity 1 Clock Phase 0 Clock Polarity 0 Clock Phase 1 SPISCS n Figure 9 1 SPI clock The meaning of each number is as follows 1 is the length of the start condition 2 i...

Page 117: ...gger interrupts When the value in the RX FIFO exceeds the RX FIFO trigger threshold in the SPI controller 1 an interrupt will be generated and a signal will be sent to the chip communication processor...

Page 118: ...pt flag will be automatically cleared Slave mode transmission timeout interrupt is triggered when the threshold is exceeded in slave mode and no clock signal is received If the TX RX FIFO overflows or...

Page 119: ...ontinuous transfer mode 1 b0 Disabled SS_n will de assert between each data frame 1 b1 Enabled SS_n will stay asserted between each con secutive data frame if the next data is valid in the FIFO 8 IGNR...

Page 120: ...U EN STO EN RXF EN TXF EN END EN RSVD TXU CLR STO CLR RSVD END CLR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD FER MASK TXU MASK STO MASK RXF MASK TXF MASK END MASK RSVD FER INT TXU INT STO INT RXF INT...

Page 121: ...r in slave mode 3 STOINT R 1 b0 SPI slave mode transfer time out interrupt triggered when SPI bus is idle for a given value 2 RXFINT R 1 b0 SPI RX FIFO ready rx_fifo_cnt rx_fifo_th interrupt auto clea...

Page 122: ...h of DATA phase 0 please refer to Timing tab 15 8 PRDP R W 8 d15 Length of STOP condition please refer to Timing tab 7 0 PRDS R W 8 d15 Length of START condition please refer to Timing tab 9 4 5 spi_p...

Page 123: ...1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD STOV Bits Name Type Reset Description 31 12 RSVD 11 0 STOV R W 12 hFFF Time out value for spi_sto_int tri...

Page 124: ...k interface 9 4 9 spi_fifo_config_1 Address 0x4000a284 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD RFTH RSVD TFTH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD RFCNT RSVD TFCNT Bits Name Type Re...

Page 125: ...Name Type Reset Description 31 0 FWDATA W x SPI FIFO write data 9 4 11 spi_fifo_rdata Address 0x4000a28c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FRDATA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 F...

Page 126: ...ll duplex asynchronous communication Data bit length can be selected from 5 6 7 8 bits Stop bit length can be selected from 0 5 1 1 5 2 bits Supports odd even no parity bits Detects wrong start bit Mu...

Page 127: ...igh The data bit width can be configured to 5 6 7 8 bit width by CR_UTX_BIT_CNT_D and CR_URX_BIT_CNT_D When CR_UTX_PRT_EN and CR_URX_PRT_EN are set the data frame adds a parity bit after the data CR_...

Page 128: ...coefficient is the count value obtained by counting the current baud rate bit width with the UART clock Because the maximum 16 bit coefficient is 65535 the minimum baud rate supported by the UART is...

Page 129: ...as follows If the FreeRun mode is not turned on the transmission behavior is terminated and an interrupt is generated when the transmission byte reaches the specified length If you want to continue th...

Page 130: ...this mode after counting the number of clocks in the starting bit width the UART module will continue to count the clocks of subsequent data bits and compare them with the start bit If it fluctuates...

Page 131: ...of data in the RX FIFO is greater than RX_FIFO_TH The bit CR_URX_RTS_SW_MODE of the URX_CONFIG register is equal to 1 The RTS level can be changed by configuring the bit CR_URX_RTS_SW_VAL of the URX_...

Page 132: ...interrupt occurs when a parity error occurs If the TX RX FIFO overflows or underflows the corresponding overflow interrupt will be triggered When the FIFO clear bit TX_ FIFO_CLR RX_FIFO_CLR is set to...

Page 133: ...ype Reset Description 31 16 TXLEN R W 16 d0 Length of UART TX data transfer Unit character byte Don t care if cr_utx_frm_en is enabled 15 14 RSVD 13 12 TXBCNTP R W 2 d1 UART TX STOP bit count unit 0 5...

Page 134: ...ached 15 12 DEGCNT R W 4 d0 De glitch function cycle count 11 DEGEN R W 1 b0 Enable signal of RXD input de glitch function 10 8 RXBCNTD R W 3 d7 UART RX DATA bit count for each character 7 IRRXINV R W...

Page 135: ...19 18 17 16 RSVD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD BIT INV Bits Name Type Reset Description 31 1 RSVD 0 BITINV R W 1 b0 Bit inverse signal for each data byte 0 Each byte is sent out LSB firs...

Page 136: ...urx_rto_timer Address 0x4000a018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD RXRTOVA Bits Name Type Reset Description 31 8 RSVD 7 0 RXRTOVA R W 8 d...

Page 137: ...transfer end interrupt set according to cr_urx_ len 0 TEIN R 1 b0 UART TX transfer end interrupt set according to cr_utx_ len 10 4 9 uart_int_mask Address 0x4000a024 31 30 29 28 27 26 25 24 23 22 21...

Page 138: ...1 b0 Interrupt clear of urx_end_int 0 TECL W1C 1 b0 Interrupt clear of utx_end_int 10 4 11 uart_int_en Address 0x4000a02c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD 15 14 13 12 11 10 9 8 7 6...

Page 139: ...ame Type Reset Description 31 2 RSVD 1 RBB R 1 b0 Indicator of UART RX bus busy 0 TBB R 1 b0 Indicator of UART TX bus busy 10 4 13 sts_urx_abr_prd Address 0x4000a034 31 30 29 28 27 26 25 24 23 22 21 2...

Page 140: ...FO 2 TFICLR W1C 1 b0 Clear signal of TX FIFO 1 UDREN R W 1 b0 Enable signal of dma_rx_req ack interface 0 UDTEN R W 1 b0 Enable signal of dma_tx_req ack interface 10 4 15 uart_fifo_config_1 Address 0x...

Page 141: ...14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD UFIWD Bits Name Type Reset Description 31 8 RSVD 7 0 UFIWD W x UART FIFO write data 10 4 17 uart_fifo_rdata Address 0x4000a08c 31 30 29 28 27 26 25 24 23 22 21...

Page 142: ...ized at the same time data transmission can prevent data from being destroyed through collision detection and arbitration BL602 includes an I2C controller host which can be flexibly configured with sl...

Page 143: ...op condition SDA generates a low to high level transition when SCL is high The waveform diagram is as follows SDA SCL S START condition P STOP condition Figure 11 1 I2C stop start condition 11 3 2 Dat...

Page 144: ...ition Figure 11 3 Master tx and slave rx Timing of master receive and slave send S SLAVE ADDRESS R W A DATA A DATA A P read n bytes acknowledge data transferred 1 Figure 11 4 Master rx and slave tx 11...

Page 145: ...setting The I2C clock is derived from bclk bus clock which can be divided based on the bclk clock Register I2C_PRD_DATA can divide the clock of the data segment The i2c module divides the data transmi...

Page 146: ...address Slave device register address indicates the register address that I2C needs to read and write to a certain register of the slave device The slave device address will be written to the registe...

Page 147: ...et to 1 I2C receives data and the host sends the process 1 Start bit 2 1 bit left from device address 0 ACK 3 Slave device address ACK 4 Start bit 5 1 bit left from device address 1 ACK 6 1 byte data...

Page 148: ...the DMA receive mode After a channel is allocated for I2C the DMA will transfer the data in the I2C_FIFO_RDATA register to the memory area When the I2C module is used with DMA the data part will be au...

Page 149: ...C_FIFO_RDATA 11 Configure the DMA destination address as the memory address to store the received data 12 Enable DMA 11 8 Interrupt I2C includes the following interrupts I2C_TRANS_END_INT I2C transfer...

Page 150: ...14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD SLVADDR RSVD SABC SAEN SCLS EN DEG EN PKT DIR MEN Bits Name Type Reset Description 31 28 DEGCNT R W 4 d0 De glitch function cycle count 27 24 RSVD 23 16 PKTLEN...

Page 151: ...MASK NAK MASK RXF MASK TXF MASK END MASK RSVD FER INT ARB INT NAK INT RXF INT TXF INT END INT Bits Name Type Reset Description 31 30 RSVD 29 FEREN R W 1 b1 Interrupt enable of i2c_fer_int 28 ARBEN R...

Page 152: ...nt rx_fifo_th interrupt auto cleared when data is popped 1 TXFINT R 1 b0 I2C TX FIFO ready tx_fifo_cnt tx_fifo_th interrupt auto cleared when data is pushed 0 ENDINT R 1 b0 I2C transfer end interrupt...

Page 153: ...25 24 23 22 21 20 19 18 17 16 PRDSPH3 PRDSPH2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PRDSPH1 PRDSPH0 Bits Name Type Reset Description 31 24 PRDSPH3 R W 8 d15 Length of START condition phase 3 23 16 PRD...

Page 154: ...15 Length of DATA phase 3 23 16 PRDDPH2 R W 8 d15 Length of DATA phase 2 15 8 PRDDPH1 R W 8 d15 Length of DATA phase 1 Note This value should not be set to 8 d0 adjust source clock rate instead if hig...

Page 155: ...Address 0x4000a384 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD RFI TH RSVD TFI TH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD RFICNT RSVD TFICNT Bits Name Type Reset Description 31 25 RSVD 24...

Page 156: ...ts Name Type Reset Description 31 0 FIWD W x I2C FIFO write data 11 9 11 i2c_fifo_rdata Address 0x4000a38c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIRD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FI...

Page 157: ...s It is widely used in many fields from measurement and communication to power control and conversion 12 2 Main features Supports 5 channel PWM signal generation Three clock sources can be selected bu...

Page 158: ...PWM source clock The clock duration is set by the register PWMn_PERIOD 15 0 n is 0 5 which is used to set the number of divided clock cycles for a PWM cycle That is the period of PWM PWM source clock...

Page 159: ...42 86 57 14 71 43 85 71 100 10 0 12 50 25 37 50 50 62 50 75 87 50 100 8 89 0 11 11 22 22 33 33 44 44 55 56 66 67 77 78 88 89 100 8 0 10 20 30 40 50 60 70 80 90 100 80 n 0 n 1 n 2 n 3 n 4 n 5 n 6 n 7 n...

Page 160: ..._config PWM2 configuration register pwm2_interrupt PWM2 interrupt register pwm3_clkdiv PWM3 clock division configuration register pwm3_thre1 PWM3 first counter threshold configuration register pwm3_th...

Page 161: ...ress 0x4000a420 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CLKDIV Bits Name Type Reset Description 31 16 RSVD 15 0 CLKDIV R W 16 b0 PWM clock division 1...

Page 162: ...escription 31 16 RSVD 15 0 THRE2 R W 16 d0 PWM sencond counter threshold can t be smaller that pwm_thre1 12 4 5 pwm0_period Address 0x4000a42c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD 15 1...

Page 163: ...ue 3 STOPMODE R W 1 b1 PWM stop mode 1 b1 graceful 1 b0 abrupt 2 OUTINV R W 1 b0 PWM invert output mode 1 0 CLKSEL R W 2 d0 PWM clock source select 2 b00 xclk 2 b01 bclk others f32k_clk 12 4 7 pwm0_in...

Page 164: ...16 RSVD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 THRE1 Bits Name Type Reset Description 31 16 RSVD 15 0 THRE1 R W 16 b0 PWM first counter threshold can t be larger that pwm_ thre2 12 4 10 pwm1_thre2 Addr...

Page 165: ...10 9 8 7 6 5 4 3 2 1 0 RSVD STOP STA STOP EN SW MODE SW FVAL STOP MODE OUT INV CLKSEL Bits Name Type Reset Description 31 8 RSVD 7 STOPSTA R 1 b0 PWM stop status 6 STOPEN R W 1 b0 PWM stop enable 5 S...

Page 166: ...0x4000a460 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CLKDIV Bits Name Type Reset Description 31 16 RSVD 15 0 CLKDIV R W 16 b0 PWM clock division 12 4 1...

Page 167: ...scription 31 16 RSVD 15 0 THRE2 R W 16 d0 PWM sencond counter threshold can t be smaller that pwm_thre1 12 4 17 pwm2_period Address 0x4000a46c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD 15 1...

Page 168: ...e 3 STOPMODE R W 1 b1 PWM stop mode 1 b1 graceful 1 b0 abrupt 2 OUTINV R W 1 b0 PWM invert output mode 1 0 CLKSEL R W 2 d0 PWM clock source select 2 b00 xclk 2 b01 bclk others f32k_clk 12 4 19 pwm2_in...

Page 169: ...16 RSVD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 THRE1 Bits Name Type Reset Description 31 16 RSVD 15 0 THRE1 R W 16 b0 PWM first counter threshold can t be larger that pwm_ thre2 12 4 22 pwm3_thre2 Add...

Page 170: ...10 9 8 7 6 5 4 3 2 1 0 RSVD STOP STA STOP EN SW MODE SW FVAL STOP MODE OUT INV CLKSEL Bits Name Type Reset Description 31 8 RSVD 7 STOPSTA R 1 b0 PWM stop status 6 STOPEN R W 1 b0 PWM stop enable 5 S...

Page 171: ...0x4000a4a0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CLKDIV Bits Name Type Reset Description 31 16 RSVD 15 0 CLKDIV R W 16 b0 PWM clock division 12 4 2...

Page 172: ...scription 31 16 RSVD 15 0 THRE2 R W 16 d0 PWM sencond counter threshold can t be smaller that pwm_thre1 12 4 29 pwm4_period Address 0x4000a4ac 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD 15 1...

Page 173: ...SW Mode force value 3 STOPMODE R W 1 b1 PWM stop mode 1 b1 graceful 1 b0 abrupt 2 OUTINV R W 1 b0 PWM invert output mode 1 0 CLKSEL R W 2 d0 PWM clock source select 2 b00 xclk 2 b01 bclk others f32k_...

Page 174: ...may cause the application to malfunction A watchdog timer can help the system recover from it If the current time exceeds the predetermined time but the dog is not fed or closed Timer which can trigg...

Page 175: ...which can be set independently to alarm when each alarm value overflows Support Free Run mode and Pre_load mode 16 bit watchdog timer Supports write password protection to prevent system abnormalitie...

Page 176: ...g mode In FreeRun mode the initial value of the counter is 0 and then counts up When it reaches the maximum value it starts counting from 0 again In PreLoad mode the initial value of the counter is th...

Page 177: ...em reset signal User reset WatchDog Counter feed Dog Figure 13 4 Watchdog timing 13 3 4 Alarm setting Each counter has three comparison values and can set whether each comparison value triggers an ala...

Page 178: ...Reset alarm Status recorded in wts Figure 13 5 Watchdog alarm mechanism 13 4 Register description Name Description TCCR Timer clock source configuration register TMR2_0 Timer2 match register 0 TMR2_1...

Page 179: ...indication register TICR2 Timer2 Interrupt clear control register TICR3 Timer3 Interrupt clear control register WICR WDT Interrupt clear register TCER Timer count enable register TCMR Timer count mod...

Page 180: ...1 2 3 WDT 2 d0 fclk 2 d1 f32k_clk 2 d2 1 kHz 2 d3 PLL 32MHz 7 RSVD 6 5 CS2 R W 2 d0 Clock Source for Timer 1 2 3 WDT 2 d0 fclk 2 d1 f32k_clk 2 d2 1 kHz 2 d3 PLL 32MHz 4 RSVD 3 2 CS1 R W 2 d0 Clock So...

Page 181: ...Description 31 0 TMR21 R W 32 hffffffff Timer2 match register 1 13 4 4 TMR2_2 Address 0x4000a518 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TMR22 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TMR22 Bits...

Page 182: ...scription 31 0 TMR31 R W 32 hffffffff Timer3 match register 1 13 4 7 TMR3_2 Address 0x4000a524 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TMR32 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TMR32 Bits Na...

Page 183: ...Address 0x4000a538 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD T2M R2S T2M R1S T2M R0S Bits Name Type Reset Description 31 3 RSVD 2 T2MR2S R 1 b0 Ti...

Page 184: ...3MR0S R 1 b0 Timer3 match register 0 status Clear interrupt would also clear this bit 13 4 12 TIER2 Address 0x4000a544 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD 15 14 13 12 11 10 9 8 7 6 5...

Page 185: ...Timer3 match register 0 interrupt enable register 13 4 14 TPLVR2 Address 0x4000a550 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TPLVR2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TPLVR2 Bits Name Type R...

Page 186: ...Pre load with match comparator 1 2 d3 Pre load with match comparator 2 13 4 17 TPLCR3 Address 0x4000a560 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD...

Page 187: ...W 1 b0 WDT enable register 13 4 19 WMR Address 0x4000a568 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WMR Bits Name Type Reset Description 31 16 RSVD 15...

Page 188: ...1 b1 no affect Read 1 b0 Watchdog timer did not cause reset because this bit was cleare Read 1 b1 Watchdog timer caused reset 13 4 22 TICR2 Address 0x4000a578 31 30 29 28 27 26 25 24 23 22 21 20 19 1...

Page 189: ...ear for match comparator 2 1 TCLR31 W 1 b0 Timer3 Interrupt clear for match comparator 1 0 TCLR30 W 1 b0 Timer3 Interrupt clear for match comparator 0 13 4 24 WICR Address 0x4000a580 31 30 29 28 27 26...

Page 190: ...D 13 4 26 TCMR Address 0x4000a588 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD TIM3 MODE TIM2 MODE RSVD Bits Name Type Reset Description 31 3 RSVD 2...

Page 191: ...1 2 interrupt mode register 1 b0 level interrupt 1 b1 pulse interrupt 13 4 28 TILR3 Address 0x4000a594 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD...

Page 192: ...CR W 1 b0 WDT timer count reset register 13 4 30 WFAR Address 0x4000a59c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WFAR Bits Name Type Reset Descriptio...

Page 193: ...scription 31 0 TCVWR2 R 32 h0 Timer2 capture value of counter 13 4 33 TCVWR3 Address 0x4000a5ac 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TCVWR3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TCVWR3 Bits...

Page 194: ...Description 31 0 TCVSYN3 R 32 h0 Timer3 synchronous value of counter 13 4 36 TCDR Address 0x4000a5bc 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WCDR TCDR3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T...

Page 195: ...anges 2020 2 13 0 9 Initial release 2020 4 20 1 0 Add related content of HBN register 2020 8 26 1 1 Add ADC and DAC 2020 12 14 1 2 Add the introduction of interrupt sources and the maximum operating s...

Reviews:

No comments