28
4.6 Advanced Chipset Features
This section allows you to configure the system based on the specific
features of the installed chipset. This chipset manages bus speeds and
the access to the system memory resources, such as DRAM and the
external cache. It also coordinates the communications between the
conventional ISA and PCI buses. It must be stated that these items
should never be altered. The default settings have been chosen
because they provide the best operating conditions for your system.
You must consider making any changes only if you discover that the
data has been lost while using your system.
Phoenix - AwardBIOS CMOS Setup Utility
Advanced Chipset Features
DRAM Timing Selectable
[By PSD]
Item Help
CAS Latency Time
[2.5]
Active to Precharge Delay
[7]
DRAM RAS# to CAS# Delay
[3]
DRAM RAS# to Precharge
[3]
DRAM Data Integrity Mode
[Non-ECC]
MGM Core Frequency
[Auto Max 266MHz]
System BIOS Cacheable
[Enabled]
Video BIOS Cacheable
[Enabled]
Memory Hole At 15M-16M
[Disabled]
Delayed
Transaction
[Enabled]
Delay Prior to Thermal
[16 Min]
AGP Aperture Size (MB)
[64]
** ON-chip VGA Setting **
On-chip
VGA
[Enabled]
On-chip Frame Buffer size
[32MB]
Boot
Display
[CRT+EFP]
Panel
Number
[1]
↑↓←
→
: Select Item
+/-/PU/PD: Value
F10: Save
Esc: Quit
F1: General Help
F5: Previous Values
F6: Fail-Safe Defaults
F7: Optimized Defaults
