enabled. Bits enabled in this register allow accessing the equivalent bits status in the
OSR and OCR registers.
Bits enabled in OER and set in OSR/OCR register will result in the Standard Operation
Status Summary bit (bit 7) in the STB register being set. See
Figure 13
.
Syntax
:STATus:OPERation:ENABle <integer>
:STATus:OPERation:ENABle?
Parameter/Response
<integer>
Allowable Values
0
– 32767 (2
15
-1)
*RST State
0
Examples
:STAT:OPER:ENAB 256
:STAT:OPER:ENAB?
:STATus:PRESET
This command presets the RTSA7500 (similar to *RST), and OSE and QSE to zero.
Syntax
:STATus:PRESET
Parameter/Response
None
:STATus:QUEStionable[:EVENt]?
This command queries the standard Questionable Status Register (QSR) for any event.
The query returns the decimal sum of the bits set in the QSR. The decimal sum is the
binary equivalent of the 16-bit mask. The last bit is unused. Any specific bit in the QSR
will only appear set if and only if its event has occurred and the corresponding bit in the
QSE is also enabled (refer to
Appendix D: SCPI Status and Event Registers
).
Caution:
This query clears all bits in the register to 0.
See
Figure 13
for the Questionable Status register bits mapping.
Syntax
:STATus:QUEStionable[:EVENt]?
Parameter
None
Response
<integer>
Output Values
0
– 32767 (2
15
-1)
*RST State
None
Example
:STAT:QUES?
:STATus:QUEStionable:CONDition?
This command queries the standard Questionable Condition Register (QCR) for any
questionable event. The query returns the decimal sum of the bits set in the QCR. The
decimal sum is the binary equivalent of the 16-bit mask. The last bit is unused. Any
specific bit in the QCR will only appear set if and only if its event has occurred and the
corresponding bit in the QSE is also enabled (refer to
Appendix D: SCPI Status and
Event Registers
). The content of the QCR remains unchanged after it is read.
The data in this register is continuously updated to reflect the most current conditions.
