SeaTrac Serial Command Interface Reference
Page 13
3.
Beacon Architecture
The diagram below shows the hardware blocks in each beacon…
Extern
al C
onnector (
5
-w
ay)
The X150 and X110 hardware are very similar, with the exception that X110 beacons do not
have the USBL receiver circuitry or transducers fitted.
3.1.
Serial Command Processor
The serial command processor sub-system consists of a series of routines running on the
processor to decode incoming serial data into messages, ensure that correct formatting is
observed and the message content is valid by means of a checksum.
The serial UART hardware features a 64-byte hardware receive buffer, from which data is
analysed and decoded started on reception of the correct “synchronisation character”.
Decoding and buffering of the command continues until the end of the message is reached at
which time it is executed by the relevant command handler function.
Further details of the serial command protocol are discussed in section 5 from page 10
onwards.
3.2.
Settings Manager and EEPROM Memory
Operational settings for the Beacon are stored in permanent non-volatile EEPROM memory and
are loaded into a working RAM copy on power up.
