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CHAPTER 2: Introductions
Figure 2-15. Elastic buffer application (data, check,
and interface control signals diagram).
Internal Clock
J1
J2
DTE Mode
DTE Mode
DCE
DCE
Internal Clock
DCD-1 controls Buffer A
DCD-2 controls Buffer B
TD
TC
RTS
RC
RD
DCD
DSR
DTR
CTS
PG
SG
RC
RD
DCD
TC
TD
RTS
DTR
DSR
CTS
PG
SG
Summary of Contents for ME260A
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