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Operation Manual
EL512.256-H3 Series Display
Beneq Oy
Olarinluoma 9
Tel. +358 9 7599 530
VAT ID FI19563372
FI-02200 Espoo
Fax +358 9 7599 5310
www.beneq.com
Finland
www.lumineq.com
Date: February 13, 2017
Document number: ED000818B
Page | 11
Notes:
1
This time is needed to display the last row and to change the frame.
2
Only rising edge is used.
3
Video Clock VCLK should be kept running.
4
The values for two bit parallel mode are 256/256 tVCLK. The number of VCLK pulses during
HS high time should be even.
5.2
Setup and hold timing
Figure 4. Setup and hold timing
Table 6. Setup and hold timing
Symbol
Description
Min
Max
tVCLK
VCLK period
33 ns
VCLK frequency
30 MHz