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beneq Lumineq EL320.240-FA3, Operation Manual

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beneq Lumineq EL320.240-FA3 Operation Manual Download Page 22

 

 

Operation Manual 

EL320.240-FA3 Display

 

 

Beneq Oy 

 

 

Olarinluoma 9

 

Tel. +358 9 7599 530

 

VAT ID FI19563372

 

FI-02200 Espoo

 

Fax +358 9 7599 5310

 

www.beneq.com

 

Finland

 

[email protected]

 

www.lumineq.com

 

 

 

 

Date: February 13, 2017

 

Document number: ED000813B

 

Page | 22 

 

 

3.7

 

Self-test mode 

The display contains a self-test mode composed of patterns displayed at the maximum frame 
rate for approximately four seconds each. Self-test mode can be useful for verifying operation 
of the display. 

The self-test patterns are as follows: yellow diagonal lines with a one sub-pixel wide 
perimeter box, all pixels red, all pixels green, and all pixels yellow. Upon power up when in 
the self-test mode, the pattern sequences are repeated three times and then the pattern 
remains in the all pixels yellow state. The self-test mode is entered by leaving LUM0 and 
LUM1 disconnected or logically high. 

3.8

 

Reliability 

The display MTBF is to be greater than 50,000 hours at maximum luminance and maximum 
input power with a 90% confidence level at 25 °C. 

3.9

 

Safety and EMI performance 

The display will not inhibit the end product from obtaining these certifications: IEC 60101-1; 
UL60950; CSA 22.2 IEC950; FCC Part 15, Subpart J, Class B; EN55022 Class B. 

 

 

EL320.240-FA3 Analog Dimming Response, Typical

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120

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LUMA voltage, volts

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Summary of Contents for Lumineq EL320.240-FA3

Page 1: ...ation Manual Beneq Oy Olarinluoma 9 Tel 358 9 7599 530 VAT ID FI19563372 FI 02200 Espoo Fax 358 9 7599 5310 www beneq com Finland lumineq beneq com www lumineq com Date February 13 2017 Document number ED000813B Page 1 EL320 240 FA3 Operation Manual ...

Page 2: ... 8 Display overlay considerations 6 3 Specifications and operation 7 3 1 Environmental 7 3 2 Over temp condition 7 3 3 Optical 8 3 3 1 Displayed colors 8 3 4 Power 10 3 5 Display interface 11 3 5 1 Video mode selection 12 3 5 2 Connector 13 3 5 3 Display input descriptions 14 3 5 4 Video mode timing SGD video mode 15 3 5 5 Video mode timing AMLCD video mode QVGA 17 3 5 6 Video mode timing AMLCD vi...

Page 3: ...een and yellow Three intensity levels in each of the red and green sub pixels generate 16 distinct colors 9 chromatically different colors black and 2 mid levels of red green and yellow The display consists of a solid state TFEL glass panel depicted below with a 124 mm diagonal active area and control electronics assembled into a space saving rugged package for easy mounting 1 1 Features and benef...

Page 4: ... a way that the bending loads might be transferred to the display during use The EL320 240 FA3 mounting tabs are designed for 3 mm screws Mounting surfaces should be flat to within 0 6 mm 0 025 Use all the mounting holes provided Failure to do so will impair the shock and vibration resistance of the final installation WARNING These products generate voltages capable of causing personal injury high...

Page 5: ...pe video interface timing Thus it is possible that a video source will be chosen This provides 18 bits of data per pixel 6 bits each for red green and blue as is common for AMLCD displays Because the EL320 240 FA3 requires just 4 bits two each for red and green of data per pixel the 18 bits would need to be mapped into 4 bits One option is to use just the two most significant bits of red and green...

Page 6: ... frame rate setting The following table lists the color levels which are dramatically distinct and most suitable for general use Color level Color description Similar color levels 3 Green 7 2 Medium Green 1 12 Red None 8 Medium Red 4 15 Yellow None 13 Orange 14 9 Brown Mustard 5 6 and 10 11 Bright Neon Green 7 0 Black None 2 8 Display overlay considerations Though not a requirement often the end s...

Page 7: ...ing non operating 100 g 6 ms half sine wave on each of six surfaces per IEC 60068 2 27 test Ea 3 2 Over temp condition The display contains a temperature sensor which measures the temperature of the circuit board at the lower left corner as viewed from the component side of the board If the board temperature exceeds approximately 100 C the display will automatically operate at its lowest luminance...

Page 8: ...al 5 Max difference of two of five points center plus four corners Luminance variation across temperature Maximum 15 Variation from 25 C to the operating extremes Luminance decrease over time Typical 6 After 10 000 hours Typical 15 After 100 000 hours 11 years Viewing angle Minimum 160 in all directions no change to contrast color or luminance Contrast ratio Typical 1000 1 0 lux ambient dark room ...

Page 9: ... 0 Black n a Off Off 1 0 0 0 1 Dim Green 450 546 Off 1 3 2 0 0 1 0 Medium Green 450 546 Off 2 3 3 0 0 1 1 Green 450 546 Off On 4 0 1 0 0 Dim Red 606 393 1 3 Off 5 0 1 0 1 Dim Yellow Brown 497 498 1 3 1 3 6 0 1 1 0 Greenish Brown 481 514 1 3 2 3 7 0 1 1 1 Neon Green 471 524 1 3 On 8 1 0 0 0 Medium Red 606 393 2 3 Off 9 1 0 0 1 Brown Mustard 524 473 2 3 1 3 10 1 0 1 0 Yellow Brown 497 498 2 3 2 3 11...

Page 10: ...y due to brightness variation Table 1 Supply voltage and power requirements Parameter Minimum Typical Maximum Abs max Display supply voltage VH 8 V 12 V 18 V Supply current with VH 8 V 0 59 A 1 16 A 1 44 A Supply current with VH 12 V 0 39 A 0 78 A 0 96 A Power consumption maximum luminance LUM0 LUM1 0 4 7 W 9 3 W 11 5 W Power consumption minimum luminance LUM0 0 LUM1 1 3 1W 6 W Quiescent power con...

Page 11: ...synchronization is provided by the VS HS and if needed DE signals Video mode detection is performed automatically The display evaluates the timing of the incoming video approximately every 25 ms and will shift on the fly between video modes as required The internal display controller utilizes a frame buffer to provide the display with the appropriate modulation on a line by line and frame by frame...

Page 12: ...quadrant of a VGA 640x480 input signal with DE determining the horizontal location of data No 1 0 AMLCD VGA Fixed AMLCD timing Displays the upper left quadrant of a VGA 640x480 input signal with the horizontal start of valid data predetermined No X 1 SGD SGD timing Horizontal start of valid data is the first VCLK after HS Yes X X Self test Displays various patterns at the maximum refresh rate rega...

Page 13: ... TCSD family of cable strips The proper connector user specified cable length and connector configuration is supplied as a single unit Consult your Samtec representative for the cable connector options Compatibility with non Samtec equivalents should be verified before use Figure 1 Data power connector Table 2 J1 Connector pin assignment Signal Pin Pin Signal VH 1 2 VH V Q 3 4 DE LUMA 5 6 LUM0 VS ...

Page 14: ...minance Control used to reduce the display luminance by reducing the voltage applied to the display phosphor If left open defaults to the luminance set by LUM0 and LUM1 LUM0 LUM1 Digital Luminance Controls used to reduce the luminance of the display by reducing the frequency at which the display is scanned VS Vertical Sync identifies the start of each frame entire screen of data Internally pulled ...

Page 15: ...ed LUMA input current 250 0 µA Note 1 All logic inputs except LUMA input are 5 V tolerant with 270 Ω series resistors 2 Input capacitance for all logic inputs except LUMA is 8 pF typical 3 DE LUM0 and LUM1 have 20 kΩ pull up resistors to 3 3 V 4 VS SHUTDOWN and V Q have 20 kΩ pull down resistors to ground 3 5 4 Video mode timing SGD video mode Item Description Min Max Units 1 HS high time 30 ns 2 ...

Page 16: ...rst row 2 The video data for a given row is clocked in prior to the falling edge of HS 3 The first 320 VCLK falling edges after the fall of HS clock in the valid data 4 If video inputs are halted the previously clocked in data will be displayed 5 Video frame dithering gray scale may cause artifacts due to the frame buffer 6 All timing measurements are made at 1 6 V 10 HS VCLK R G data VS HS First ...

Page 17: ...S to DE phase difference 2 HS period 340 VCLK periods 4 DE set up time 5 VCLK period 10 ns 5 VCLK frequency 7 MHz 6 R G data set up to VCLK 5 ns 7 R G data hold from VCLK 10 ns 8 VS low width 2 34 HS periods 9 VS to HS phase difference 0 HS period HS low time ns 10 Vertical start position After 7 HS rising edges DE high time 2 HS period 10 VCLK periods HS period 50 µs VS period 251 280 HS periods ...

Page 18: ...S to VCLK phase difference 10 VCLK period 10 ns 5 VCLK frequency 7 MHz 6 R G data set up to VCLK 5 ns 7 R G data hold from VCLK 10 ns 8 VS low width 2 34 HS periods 9 VS to HS phase difference 0 HS period HS low time ns 10 Vertical start position After 7 HS rising edges HS period 50 µs VS period 251 280 HS periods HS VCLK R G data VS HS Horizontal Timing Vertical Timing data for first pixel 9 8 6 ...

Page 19: ...o DE phase difference 44 HS period 664 VCLK periods 4 DE set up time 5 VCLK period 10 ns 5 VCLK frequency 28 33 MHz 6 R G data set up to VCLK 5 ns 7 R G data hold from VCLK 10 ns 8 VS low width 2 34 HS periods 9 VS to HS phase difference 0 HS period HS low time ns 10 Vertical start position After 34 HS rising edges DE high time 2 HS period 10 VCLK periods HS period 30 µs VS period 515 560 HS perio...

Page 20: ... VCLK phase difference 10 VCLK period 10 ns 5 VCLK frequency 28 33 MHz 6 R G data set up to VCLK 5 ns 7 R G data hold from VCLK 10 ns 8 VS low width 2 34 HS periods 9 VS to HS phase difference 0 HS period HS low time ns 10 Vertical start position After 34 HS rising edges HS period 30 µs VS period 515 560 HS periods HS VCLK R G data VS HS Horizontal Timing Vertical Timing data for first pixel 9 8 6...

Page 21: ...control characteristics LUM0 logic level 0 1 0 LUM1 logic level 0 0 1 Approximate frame rate Hz 325 240 180 Approximate relative luminance 100 74 55 If the dimming obtained from digital dimming is insufficient analog luminance control the LUMA input may be used to adjust the luminance further downward Connection of a 50 kΩ variable resistor between LUMA and GND will give a brightness range of appr...

Page 22: ... box all pixels red all pixels green and all pixels yellow Upon power up when in the self test mode the pattern sequences are repeated three times and then the pattern remains in the all pixels yellow state The self test mode is entered by leaving LUM0 and LUM1 disconnected or logically high 3 8 Reliability The display MTBF is to be greater than 50 000 hours at maximum luminance and maximum input ...

Page 23: ...l details the Mechanical Outline drawing is available at www beneq com Note the 20 56 mm component envelope This is the depth required by the display to ensure no interference with display board components which are up to 12 19 mm in height above the board surface While tall components are the minority Beneq reserves the right to relocate components within the constraints of the component envelope...

Page 24: ...y Olarinluoma 9 Tel 358 9 7599 530 VAT ID FI19563372 FI 02200 Espoo Fax 358 9 7599 5310 www beneq com Finland lumineq beneq com www lumineq com Date February 13 2017 Document number ED000813B Page 24 Figure 2 Display dimensions millimeters 0 25 mm ...

Page 25: ...Repair or replacement of goods is seller s sole obligation and buyer s exclusive remedy for all claims of defects If that remedy is adjudicated insufficient Seller shall refund buyer s paid price for the goods and have no other liability to buyer All warranty repairs must be performed at seller s authorized service center using parts approved by seller Buyer shall pay costs of sending goods to sel...

Page 26: ...mmonly known as RoHS II or RoHS Recast which compared to RoHS keeps the restrictions on the original six hazardous substances including lead Pb in electronic equipment It also expands these restrictions to previously exempted categories including medical devices and monitoring and control instruments Beneq part number with an LF suffix designation indicates RoHS compliance as shown on the part num...

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