Operation Manual
EL320.240-FA3 Display
Beneq Oy
Olarinluoma 9
Tel. +358 9 7599 530
VAT ID FI19563372
FI-02200 Espoo
Fax +358 9 7599 5310
www.beneq.com
Finland
www.lumineq.com
Date: February 13, 2017
Document number: ED000813B
Page | 20
3.5.8
Video mode timing—AMLCD video mode, VGA, fixed
Item
Description
Min.
Max.
Units
1
HS low time
2
200
VCLK periods
2
HS to VCLK phase difference
10
VCLK period - 10
ns
5
VCLK frequency
28.33
MHz
6
R/G data set up to VCLK
5
ns
7
R/G data hold from VCLK
10
ns
8
VS low width
2
34
HS periods
9
VS to HS phase difference
0
HS period – HS low time
ns
10
Vertical start position
After 34 HS rising edges
HS period
30
µs
VS period
515
560
HS periods
HS
VCLK
R/G data
VS
HS
Horizontal Timing
Vertical Timing
data for first pixel
9
8
6
7
5
10
1
horizontal invalid data period
clock edge C1
first valid clock =
clock edge C104
R/G data
vertical invalid data period
data for first line
Line 1
Line 2
Line N
2
