REF: BBONEBLK_SRM
BeagleBone Black System
Reference Manual
Rev A5.2
Page 51 of 108
Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during power-
down. Input buffers (excluding CKE and RESET#) are disabled during SELF REFRESH.
CKE is referenced to V
REFCA
.
DDR_CKE
3
DDR_CLKn
3
DDR_CLK
3
DDR_WEn
3
DDR_CASn
3
DDR_RASn
3
DDR_CSn
3
DDR_RESETn
3
C124
0.1uf ,6.3V
DDR_DQM0
3
DDR_DQM1
3
4Gb(512MB) DDR3L
DDR_A15
R97
1.5K,1%
R96
10K,1%
R100
10K,1%
R99
240E
R98
10K,1%
C123
0.001uf ,50V
DDR_ODT
U12
MT41K256M16HA -125:E
CK
J7
CKn
K7
CKE
K9
CSn
L2
RASn
J3
CASn
K3
WEn
L3
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10
L7
A11
R7
A12
N7
A13
T3
A14
T7
BA0
M2
BA1
N8
BA2
M3
DQ0
E3
DQ1
F7
DQ2
F2
DQ3
F8
DQ4
H3
DQ5
H8
DQ6
G2
DQ7
H7
ODT
K1
VSS1
A9
VSS2
B3
VSS3
E1
VSS4
G8
VSSQ4
D8
VSSQ3
D1
VSSQ2
B9
VSSQ1
B1
VSSQ5
E2
VDDQ1
A1
VDDQ2
A8
VDDQ3
C1
VDDQ4
C9
VDDQ5
D2
VDD1
B2
VDD2
G7
UDQSn
B7
UDM
D3
LDM
E7
LDQSn
G3
UDQS
C7
LDQS
F3
DQ8
D7
DQ10
C8
DQ11
C2
DQ14
B8
DQ12
A7
DQ15
A3
DQ13
A2
VDD9
D9
VSSQ6
E8
VDDQ7
E9
VDDQ8
F1
VSSQ7
F9
VSSQ8
G1
VSSQ9
G9
VREF_DQ
H1
VDDQ9
H2
VDDQ10
H9
NC1
J1
NC2
J9
VSS5
J2
VSS6
J8
VDD4
K2
VDD5
K8
NC3
L1
ZQ
L8
NC4
L9
VSS7
M1
A15
M7
VREF_CA
M8
VSS8
M9
VDD6
N1
VDD7
N9
VSS9
P1
VSS10
P9
VDD8
R1
VDD3
R9
VSS11
T1
RESET#
T2
VSS12
T9
DQ9
C3
VDDS_DDR
DGND
DGND
DGND
DDR_D10
DDR_D11
VDDS_DDR
DDR_D8
DDR_D15
DDR_D13
DDR_D14
DDR_D9
VDDS_DDR
DGND
DDR_D12
DGND
DDR_ODT
3
VDDS_DDR
DDR_DQS0
3
DDR_DQSN0
3
DDR_D1
DDR_D2
DDR_D3
DDR_DQSN1
3
DDR_DQS1
3
DDR_D4
DDR_D0
DDR_D7
DDR_D5
DDR_D6
DDR_A1
DDR_A3
DDR_A[15..0]
3
DDR_BA[2..0]
3
DDR_A6
DDR_A2
DDR_A8
DDR_A9
DDR_A4
DDR_A0
DDR_D[15..0]
3
DDR_A7
DDR_A13
DDR_A14
DDR_A10
DDR_A5
DDR_BA1
DDR_BA2
DDR_BA0
DDR_A11
DDR_A12
DDR_A[15..0]
ZQ
DDR_BA[2..0]
DDR_VREF
Figure 30.
DDR3L Memory Design
Chip Select Line:
CS# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS# is registered HIGH. CS#
provides for external rank selection on systems with multiple ranks. CS# is considered
part of the command code. CS# is referenced to V
REFCA
.