BCM Advanced Research
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DRAM (DIMM) Sockets
Connection to the main system DRAM can be done via two (2) DIMM connectors on
the system PWA.
Reference:
DIMM0, DIMM1
Connector Type:
female, 168 pin DIMM, in-line connector
Connector Part Number:
Berg. 91145-60024 (Or equivalent)
System BIOS
The system and video BIOS are stored in a 2M-bit (256Kx8) Flash Memory device. The
system BIOS is always shadowed and cached.
L2 Cache Subsystem
The Pentium
II processor cartridge provides an unified 0KB or 512KB second level (L2)
cache to complement the level one data and instruction (L1) internal caches. The L2 cache
is Direct-Mapped non-sectored, supporting the Write Back policy architecture.
Table 2.4. L2 Cache latency with Burst SRAM
Cycle Type
Clock Count
Burst Read
X-1-1-1
Burst Write (Write-back)
X-1-1-1
Single Read
X
Single Write
X
Pipelined Back-to-Back Burst Reads
X-1-1-1,1-1-1-1
1
1
: The back-to-back cycles do not account for CPU idle clocks between cycles
Cacheable and Non-Cacheable Regions
The system caches the following regions:
•
All system memory, including 0 to 640 KB and all memory present above 1
MB up to 1GB.
•
System and integrated video controller BIOS.
The system does not cache the following regions:
•
The video memory block from A0000 to BFFFF.
