BCM Advanced Research
11
1 Introduction
This section provides an overview for the MicroATX Pentium
II based PCI/ISA Printed Wiring Assembly
(PWA) code-named "IN440EX". It describes functional blocks and their relationship. The following diagram
shows the functional blocks
Overview
The IN440EX is an implementation of BCM Advanced Research for a High-Volume MicroATX motherboard featuring
these subsystems:
•
Intel Pentium™ II MMX Processor cartridge support through the SLOT 1 connector
•
Intel 82440EX PCIset: 82443EX (“PAC” PCI A.G.P. Controller) and 82371SB (“PIIX4” PCI-ISA-IDE
Xcelerator)
•
Accelerated Graphics Port “AGP” connector
•
PCI IDE Bus Master interface
•
Embedded advanced I/O support
•
System Management Logic
•
Advanced multiple Audio interface
•
USB (Universal Serial Bus)
•
System Monitoring Hardware
•
MicroATX form-factor motherboard
The targeted Operating Systems for the IN440EX are: Windows 95, Windows 98 and Windows NT.
Processor Subsystem
The IN440EX has provisions to support the following processors: Intel Pentium™ II Processor with MMX™
technology (Deschutes) operating at 333/66, 300/66, 266/66 and 233/66 MHz. The Processor speeds are selectable
with a four, (4) jumper block combination for the bus-to-core frequency ratio and CPU bus speed. The bus-to-core
ratio is either 2/7, 1/4, 2/9 or 1/5 yielding the bus/core frequency; 66/233, 66/266, 66/300 or 66/333 MHz respectively.
High-performance features, including pipelined 32-bit addressing, 64-bit data, 16KB/16KB Instruction/Data Write-
back or Write-through 2-way set associative primary cache. 0KB/512KB Write-back direct mapped secondary cache on
the CPU Cartridge using a Back-Side-Bus (BSB). Two (2) Memory DIMM for support of SDRAM.
Two onboard DC/DC converters supply the +2.5 Volts for the CPU I/O voltage and the +1.5 Volts GTL+ bus voltage
(VTT). An on-board switching power converter supplies the CPU core voltage (VCORE), the switcher supports the
Pentium
II Voltage-ID pins for auto-voltage programming of the switcher supply.
Cache Subsystem
The cache and control functions are part of the Pentium
II Processor. The cache SRAM interface is through the
processor’s Back-Side-Bus (BSB) and is included within the CPU cartridge.
The IN440EX can accept either the Pentium
II cartridge with 512KB of second level (L2) Pipelined Burst SRAM
cache. The Pentium
II second level cache supports a direct mapped organization with a write-back policy, providing
all necessary snoop functions and inquire cycles. Cacheability of the entire memory space in the first level cache is
supported. For the second level cache only the first 512MB of main memory is cacheable, and only main memory
controlled by the PAC DRAM interface will be cached, PCI and ISA memory is not cached.
