Date : 10/02/98 R7621127
Sync+Vertical Deflection
R7621127
21
Technical description
the IC itself, but the latter has only a limited range of approx. 1.2 khz. Therefore,
it serves as a fine lock for the frequency. An additional PLL (4046B), IC6, is used
to coarse lock the frequency first.
The 4046B consists of two digitally controlled phase comparators. For this
application only the second one is used. The
SIGN
input, pin 14, is the line
oscillator
HOSC
of the TDA2595, and the
COMP
input is the comp. sync
HS/CS'
.
The corresponding output is
PC2
, pin 13, a three-level state output.
If the output is open (high impedance), the voltage is set at 6 volts with R58/R59.
This voltage can increase or decrease by the push-pull output of the IC. The voltage
is buffered and reaches pin 5 of a voltage comparator in IC3. The other input , pin
6, is fixed by R45/R39. The output of the comparator switches on or off the fet Q4
which allows the transfer of the regulating voltage to the TDA2595 when on
(shorted).
b) Coincidence detector
The HOSC (squarewave) switches on and off the transistor Q10. When switched
on, any pulse arriving at the base of Q8 is clamped at ground and cannot switch
on the latter. When the frequency and/or phase of the line oscillator is different from
the composite sync, these pulses arrive on the base of Q8 at the moment Q10 is
off. These pulses then switch on and off Q8 and discharge C27 which decreases
the voltage at pin 6. The voltage at the other input cannot drop lower than 6 volts
due to the zenerdiode Z4.
Consequently, the output pin 7 switches high to forward biases Q10. The latter
connects the buffer-output with the integrating OPAMP (1-2-3 of IC3).
c) Locking of the oscillator
The regulating voltage at pin 1 of IC3 drives Q1 via an adjustable zener IC5. The
efficiency of the circuit is thus automatically adapted to the line frequency. The
collector-emitter current of Q1 determines the frequency of the line oscillator in the
TDA2595.
The line oscillator is corrected until it is locked to the comp. sync frequency. The
PLL output is now disconnected from the OPAMP input since the coincidence
circuit turns off the fet Q4.
From this point on, the fine frequency lock in the TDA2595 takes over and adjusts
the line oscillator until the exact frequency and phase is reached.
As the coarse tuning voltage is lost now, the PLL output pin 17 of the TDA2595,
feeds now pin 2 of the integrating OPAMP IC3 to establish and maintain the fine
tuning loop.
In the locked state, this PLL output is 6 volts. As pin 3 of the OPAMP is set at 6
volts with R8 / R13, the action of the OPAMP continues up to the moment the
oscillator is locked to the centre of the hold range of the PLL.
d) Frequency mode switching - Tracking Hor Freq.
The horizontal frequency tracked voltage TRACKING HOR FREQ is smoothened
with R73/C47 and compared with an adjustable voltage from the slider of P1
(Hysteresis centre switching relays).
The H FREQ MODE output is high or low depending on :
- the TRACKING HOR FREQ voltage, thus on the tuned frequency
The oscillator in the TDA2595
is locked to the centre fre-
quency by a PLL system in
Summary of Contents for GRAPHICS 1209S
Page 4: ...BARCO PROJECTION SYSTEMS GRAPHICS 1209S 90 00972 230V AC 90 00977 120V AC SAFETY NOTICE...
Page 9: ...BARCO PROJECTION SYSTEMS GRAPHICS 1209S 90 00972 230V AC 90 00977 120V AC GENERAL INFORMATION...
Page 28: ...BARCO PROJECTION SYSTEMS GRAPHICS 1209S 90 00972 230V AC 90 00977 120V AC SERVICE SHEETS...
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