Date : 10/02/98 R7625115
Controller module
R7625115
13
Technical description
PLL
The PLL consists of the digitally edge controlled phase comparator IC15, the low pass
filter around IC14, the VCO (Q1 - Q12) and the internal divider in the ASIC. The VCO
is a sawtooth generator. C36 is charged up via Q5, driven in the base with the low pass
filter output. Note that 0 volts on the base means the maximum frequency. The VCO_0/
1/2 lines can turn on transistors and then additional current is available for the
generator.
Via the emitterfollower Q1 and the buffer in IC39, the pixelclock is applied to the CPP
input of the ASIC. The PLL phase comparator has a double task. Tune the frequency
of the VCO to a multiple of the line frequency and lock the position of the text to the
deflection.
The active line period is divided into 256 pixels to position 32 characters on a line in
the low frequency range and into 512 pixels (64 characters) in the high freq. range (see
Hor defl module) .
The
HFM
line informs the processor and thus the PLL on the flyback time, this
information is needed to determine the pixel frequency of the PLL.
Coincidence
The coincidence of the line oscillator is an important information for the controller. At
starting up, the controller always generates first internal sync, which must lead to a
coincidence situation.
If an external source is selected then, the controller waits for coincidence and the
timings of the selected source. These timings are needed to choose the memory block
corresponding with the source. If the coincidence is not active, the projector remains
blanked (black screen).
the communication lines with the switcher / selector RCVDS800 or RCVDS05.
The RDY line (Ready line) informs the microprocessor on the status of the switcher
(powered up or powered down).
ASIC
The ASIC IC17 integrates different functions and is custom made for this application.
This chip is amongst others responsible for the generation and synchronisation of the
text that must be projected on request. The text or pixel information is loaded by the
controller into the RAM IC18. Eight bytes are loaded into the RAM via the ASIC during
the HFB time. (For that reason, the controller cannot start up when there are no HFB
pulses available from the ASIC).
When an external source is selected, the ASIC measures 'frequently' the line and
vertical frequencies and informs the main processor if there are changes (change of
resolution mode or change of source....).
The pixelclock, generated by the VCO of the PLL, is sent to the ASIC where it is divided
down to
HFB
and returned to the phase comparator of the PLL.
When an internal pattern is selected, required by the user or automatically at starting
up, the ASIC generates sync signals HSO and VSO.
The R, G and B together with the INSERT are buffered with IC31 and further proceed
to the RGB INPUT + SW module.
Summary of Contents for GRAPHICS 1209S
Page 4: ...BARCO PROJECTION SYSTEMS GRAPHICS 1209S 90 00972 230V AC 90 00977 120V AC SAFETY NOTICE...
Page 9: ...BARCO PROJECTION SYSTEMS GRAPHICS 1209S 90 00972 230V AC 90 00977 120V AC GENERAL INFORMATION...
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