Page 4 of 5 - 22 March 2005
Technical specifications are subject to change without prior notice
Rate allocator
This optional module is dedicated to regulate the output of the encoding IP core to the bit rate specified
by the user. This module makes use of a patented rate allocation algorithm, exploiting statistical
information available at the motion estimation to improve its efficiency and provide a more stable
stream bit rate and quality.
This module is implemented as software code able to run on a simple processor (Nios or Microblaze for
instance). The rate allocator can also be customized to be mapped as a 100% hardware block.
Implementation data
The following table details implementation results of the BA131MPEG4E core on various FPGA
technologies. The core is 100% RTL and ASIC technologies can also be mapped. Performance figures
enable real-time encoding for all Simple Profile L1 to L5 levels.
Device
Logic
# of
Clk
Performance
(MHz)
Needed Resource
Troughput
(Msamples/s)
1)
Altera
EP1S25C5
2)
18000 LE’s
1 100
92 M4K,
16 DSP Multipliers
18.2
Xilinx
XC2V2000-4
9000
Slices
1 100
30 RAMB16,
16 MULT18x18
18.2
1) Results for typical compression, as measured on difficult video sequences
2) Estimated (contact us for latest figures)
Pinout description
Name
I/O
Size
Comments
Global
CLK I
1
Clock
RESET
I
1
Global asynchronous reset
CPU Interface
XENA I
1
Chip
Select
XWEA I
1
Access
direction
XADDR I
5
Address
lines
XQ O
32
Read
data
XD I
32
To-be-written
data
Pixel Interface
PEMPTY
I
1
Pixel not ready
PQ I
8
Pixel
data
PRE O
1
Pixel
read
enable
Compressed Data Interface
CWE
O
1
Compressed data strobe
CDATA O
8
Compressed
data
CFULL
I
1
Compressed data not ready flag
Memory Interface (read queue)
MRQFULL
I
1
Read request queue full
MRQPUSH
O
1
Push read request
MRQADDR
O
32
Read request address
MRQEMPTY
I
1
Read data queue empty
MRQPOP
O
1
Pop read data
MRQRD
I
32
Read data (16-word burst)
Memory Interface (write queue)
MWQFULL
I
1
Write request queue full
MWQPUSH
O
1
Push write request
MWQADWD
O
32
Write request address and write data (16-word burst)
