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Page 5 of 5 - 22 March 2005 

Technical specifications are subject to change without prior notice          

 

 

 

 

Barco Silex overview 

 

Barco Silex is a micro-electronic design house located in Belgium and France belonging to the Belgian 

Barco group. 

 
Barco Silex offers a complete portfolio of high-end design services, from ASIC/FPGA design to advanced 

SoC/SoPC based system development, IP-core design and board design in the fields of: 

 

 

image processing  

 

communications 

 

consumer electronics 

 

industrial electronics. 

 

Barco Silex IP products 

 
Barco Silex design expertise is also made available through a wide portfolio of IP products, with a strong 

focus on high performance, standardized image processing and encryption functions. 

All these IP cores have been designed and fully validated by Barco Silex and are hardware proven, 

which guarantees high IP quality as well as best support during your integration phase.   
 

Deliverables include: 

 

RTL Code or netlist (depending on license type) 

 

Functional simulation testbench 

 

Synthesis script 

 

Full documentation 

For some of them, we can also provide you with simulation models and a design kit. 

 

These "off the shelf", high quality IP cores provide you with the fastest and most efficient way of 

integrating complex functionalities on FPGAs or ASICs, while meeting short time to market constraints. 
 

More information 

 

Order-reference: BA131MPEG4E 
 

For additional information and other IP products contact: 

Barco – Silex 
e-mail: 

[email protected]

 

http://www.barcodesignservices.com

 

 

or the local Barco Silex design centers: 

 

 

Belgium 

France 

 

Scientific Park 

ZI Peynier- Rousset 

 

 

Rue du Bosquet 7 

Route de Trets Imm CCE 

 

1348 Louvain-la Neuve  13790 Peynier 

 +32(0)10/45.49.04  +33(0)44/216.41.06

 

 

Summary of Contents for BA131

Page 1: ...onstant Bit Rate option available through Microblaze or Nios code with advanced bit rate regulation algorithm using statistical information available from the motion estimation engine Easy synchronous pixel and stream interfaces Easy control and status interface through simple CPU interface Off chip reference frame store with easy memory interface pluggable to any custom memory controller SRAM or ...

Page 2: ...otion estimation engine Applications Video broadcast Security and Surveillance Multimedia streaming over TCP IP Mobile communications Technical description Figure 1 illustrates a simplified block diagram of the BA131MPEG4E IP showing the internal modules and its interfaces The video data is organized in macroblocks under YUV format 4 2 0 resolution One macroblock is made of 4 luminance blocks 8x8 ...

Page 3: ...enting the frequency contents of the original block of data This is then quantized using a scalar quantizer The quantization factor is programmable by the user allowing him to set the quality level The AC DC predictor is used for I VOPs and performs a prediction of the first line or the first column of the quantized matrix based on the transformed blocks situated on the left and on top of the curr...

Page 4: ...rformance MHz Needed Resource Troughput Msamples s 1 Altera EP1S25C52 18000 LE s 1 100 92 M4K 16 DSP Multipliers 18 2 Xilinx XC2V2000 4 9000 Slices 1 100 30 RAMB16 16 MULT18x18 18 2 1 Results for typical compression as measured on difficult video sequences 2 Estimated contact us for latest figures Pinout description Name I O Size Comments Global CLK I 1 Clock RESET I 1 Global asynchronous reset CP...

Page 5: ...d and fully validated by Barco Silex and are hardware proven which guarantees high IP quality as well as best support during your integration phase Deliverables include RTL Code or netlist depending on license type Functional simulation testbench Synthesis script Full documentation For some of them we can also provide you with simulation models and a design kit These off the shelf high quality IP ...

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