Page 2 of 5 - 22 March 2005
Technical specifications are subject to change without prior notice
General description
The MPEG-4 encoder is a hardware module optimized for FPGA technologies, making use of a limited
number of logic resources and being able to encode a 4CIF (704x576) sequence in real time.
It is fully compliant with the Video part of ISO/IEC 14496-2. All visual tools of the Simple Profile are
implemented, including full support of I-VOP (intra-coded frames, without motion estimation) and P-VOP
(predictive-coded frame, with motion estimation on previously encoded frame). The core is a good
compromise between coding efficiency (resulting in lower bit rate for same quality), logic complexity
and coding throughput, thanks to the use of an efficient motion estimation algorithm (directional
search) leading to fast and precise matching, at half pixel resolution, of blocks between the current
frame and its reference.
Supported image resolutions include pre-defined levels Level1 to Level5(QCIF/CIF/VGA/SDTV) and
custom definitions up to 4CIF (704x576). The core can be customized to provide support for even larger
resolutions, such as HD format.
The core features a Variable Bit Rate mode (VBR mode: fixed, user-specified quality). It can optionally
also provide Constant Bit Rates (CBR mode: with regulation of the output bit rate) by using an external
small microprocessor running a rate allocation algorithm (such as Nios or Microblaze). When used in
CBR mode, the core delivers high-quality regulation thanks to its patented rate allocation algorithm
making use of statistical information available at the motion estimation engine.
Applications
•
Video broadcast
•
Security and Surveillance
•
Multimedia streaming over TCP/IP
•
Mobile communications
Technical description
Figure 1 illustrates a simplified block diagram of the BA131MPEG4E IP showing the internal modules and
its interfaces.
The video data is organized in macroblocks under YUV format (4:2:0 resolution). One macroblock is
made of 4 luminance blocks (8x8), 1 Cb block (8x8) and 1 Cr block (8x8). The video data is sent to the
core through its video interface in macroblock raster scan order. It generates the compressed stream at
its Compressed Data Interface. The stream contains fully compliant headers and is regulated to a given
bit rate if the CBR option is enabled (together with external microprocessor running the rate allocation
algorithm).
The encoder has a generic interface to a memory controller, allowing the connection to any custom
memory controller. Thanks to the burst nature of data transfers at this interface, the core can be used
with simple SRAM but also SDRAM or DDR SDRAM. The core can be delivered with a standard SRAM
controller; a suitable SDRAM controller is separately available. The core has been optimized in order to
minimize the amount and bandwidth of off-chip memory. A single frame needs to be stored and
accesses are reduced to 1 read and 1 write per input sample.
The encoder has a simple generic interface to an external CPU in order to configure the various
parameters of the core and to monitor the status of the encoding process.
The following sections describe the modules constituting the BA131MPEG4E core as depicted under
Figure 1.
Motion estimation
The first module of the core is the motion estimation engine. This module is bypassed for Intra-coded
pictures (I-VOP), which are not coded with reference to any other picture.
