PT-6IFB
SYSTEM BOARD
AWARD BIOS SETUP
I.
6
Read-Around-Write
: Enabled
PCI Burst Write Combine
: Enabled
PCI-To-DRAM Pipeline
: Enabled
ESC : Quit
: Select Item
CPU-To-PCI Write Post
: Enabled
F1 : Help
PU/PD/+/- : Modify
CPU-To-PCI IDE Posting
: Enabled
F5 : Old Values (Shift)F2 : Color
System BIOS Cacheable
: Disabled
F7 : Load Setup Defaults
Video RAM Cacheable
: Disabled
Fig. 5-5 CHIPSET FEATURES SETUP screen.
WARNING :
The CHIPSET FEATURES SETUP in this screen are provided so that
technical professionals can modify the Chipset to suit their requirement.
If you are not a technical engineer, do not use this program !
Auto Configuration :
When "Enabled", this parameter automatically enters and locks some of the optimum
values for the chipset and CPU. Otherwise, this parameter allows the values of these
fields could be changed.
DRAM Speed Selection :
When "Auto Configuration" is "Enabled", this field provides two suit of the optimal
values for the chipset and CPU, depends on the DRAMs' speed, you can select "70 ns"
or "60 ns". "70ns" maybe caused your system more stable, but also decrease the
system's performance.
DRAM ECC/PARITY Select :
This system board provides a DRAM ECC (Error Checking and Correcting) or Parity
function for DRAM subsystem. If all your DRAM SIMM modules have true parity bit,
you can set this field to ECC or PARITY to monitoring the DRAMs access status, but if
your DRAM modules don't all have parity bit, leave this field on default setting of
Disabled to avoid any error movement occurs.
Read-Around-Write :
The default setting of Enabled will increase the execution efficiency of the processor. It
allows the processor to execute read commands out of order if there is no dependence
between these read and other write commands.
PCI Burst Write Combine :
The default setting of Enabled will increase the efficiency of the PCI bus by combining
several CPU to PCI write cycles into one. VGA performance is increased by this action.
