SBC856A1 Series All-in-One POS Board User’s Manual
Award BIOS Utility
41
DRAM Clock / Driver Control
Phoenix – AwardBIOS CMOS Setup Utility
DRAM clock / Drive Control
Current FSB Frequency
100 MHz
Item
Help
Current DRAM Frequency
133MHz
DRAM Clock
By SPD
Menu
Level
f
DRAM Timing
By SPD
DRAM Cas Latency
2.5
Bank Interleave
Disabled
Precharge to Active (Trp)
3T
Active to Precharge (Tras)
6T
Active to CMD (Trcd)
3T
DRAM Command Rate
2T Command
ÇÈÆÅ
: Move Enter: Select +/-/PU/PD: Value F10: Save ESC: Exit F1: General Help
F5: Previous Values F6: Fail-Safe Defaults F7: Optimized Defaults
z
Current FSB Frequency
This field shows the detected FSB of the CPU.
z
Current DRAM Frequency
This field shows the detected frequency of the DRAM.
