CMD-5xx 08/07/02
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PM-565/6 Hardware Options
JP1, 2, 3, 4 Option Jumpers
BDM Port operating voltage selection. All 4 jumpers must be optioned the same for correct interface levels on associated signals.
The selection of 2.6V or 3.3V operation is dependent on the BDM Pod to be connected to the BDM_PORT. Default setting is 3.3V
which selects the proper voltage outputs for most common BDM Pods. Refer to BDM Pod information for correct setting.
VDDSRAM Option
VDDSRAM1, 2, and 3 pins are connected to the 2.6V supply on the PM-565 by zero ohm resistor R5 on the PM565/6 board. To
apply a different source for the VDDSRAM, the R5 resistor should be removed and the CMD565/6 POWER_PORT connection for
VDDSRAM should be used for applying the new source input.
XFC Filter Capacitor Option
PM565/6 capacitor C5 provides the XFC filtering for the PLL circuits. The capacitor should be changed by the user if PLL locking
problems are experienced at the frequency of operation selected. Current value is 3.3nF. Refer to MPC565/6 manual for more
information.
VDDSYN Voltage Source
The VDDSYN connection on the MPC565/6 provides zero ohm resistor R11 for isolation. To apply a different voltage source for
low power back-up operations, R11 should be removed and the new source applied to the CMD565/6 POWER_PORT pin for the
VDDSYN connection.
KAPWR Voltage Source
The KAPWR connection on the MPC565/6 to the PM565/6 2.6V supply is provided by zero ohm resistor R12. To apply a different
voltage source for low power back-up operations, R12 should be removed and the new source applied to the CMD565/6
POWER_PORT pin for the KAPWR connection.
VRH and VRL QADC Reference Supplies
PM565/6 zero ohm resistors R9 and R10 provide connection to PM565/6 VDDA and VSSA for VRH and VRL reference signals
respectfully. One or both of these resistors can be removed to apply an external reference voltage to the CMD561-4 QADC_A Port.
EPEE and BOEPEE CUTAWAY #3
The PM565/6 board has the EPEE and BOEPEE signals connected by CUT_AWAY pad #3. This connection is for NEXUS port
programming of the CMFI flash. This connection will cause the CONFIG_SW position 5 or 6 to enable both signals. If this
operation is not desired by the user, cut the CUT-AWAY #3 pad to isolate the signals from each other.
PORESET CUT-AWAY #6
The PM565/6 board provides a 5V Voltage Level Detector to operate the PORESET signal from power on and provide a 300ms
PORESET signal duration when the PORESET switch is applied. For external application of a PORESET signal, the user should
cut the CUT-AWAY #6 pad and use the CMD565/6 CONTROL_PORT connection to apply the external PORESET signal.
VDDA and VSSA QADC Primary Supplies
Resistors R7 and R8 provide isolation of VDDA and VSSA supply voltages respectfully. One or both of these resistors can be
removed to apply an external supply voltage to the QADC.
VFLASH Voltage Source
The VFLASH pin of the MPC565/6 is connected to the +5V supply by resistor R6 on the PM565/6-T board. To apply a different
voltage source to the internal flash array, R6 should be removed and the new source applied to the CMD565 POWER_PORT pin for
the VFLASH connection.
VDDRTC Voltage Source
The VDDRTC pin of the MPC565/6 is connected to the +2.6V supply by resistor R47 on the PM565/6-T board. To apply a
different voltage source to the VDDRTC pin, R47 should be removed and the new source applied to the CMD565 POWER_PORT
pin for the VDDRTC connection.
VFLS0 / 1 Signal Options -
The VFLS0 and VFLS1 signals provided to the BDM_PORT are the default IWP0 and IWP1 shared
signal pins. The default signal connections are provided by 0 ohm resistors R50 and R48 respectfully. To change from the default
VFLS0 and VFLS1 signals to the alternate MGPIO port 3 and 4 provided signals, resistors R50 and R48 should be removed and 0
ohm resistors or jumper wire installed in the R51 and R49 resistor positions.
