CMD-5xx 08/07/02
12
Memory Device / Bank Selection and Configuration.
The CMD-5xx board has three external memory banks and a PRU that provide:
•
512K x 32bit (2MByte) Synchronous Static RAM (U2 – U5)
•
1M x 32bit (4MByte) Burstable Flash EEPROM (U13 - U14)
•
MEM Option Sockets for 8 or 16bit wide EPROM memory (U15 – U16)
•
Port Replacement Unit (PRU) with LCD and Keypad Ports
Each memory bank can be configured individually to operate from the MPC5xx chip selects. Caution should be used not to place
more than one memory bank on the same chip select or properly configure the chip select to operate the Memory Devices in the
memory bank correctly.
Failure to observe precautions may render the external memory bus inoperable and cause the user
great anxiety and grief.
The MAP Switch, MEM_EN option jumper, and PRU_EN option jumper connect MPC5xx chip selects to the different memory
banks. If memory access problems occur, the settings of these options and the associated chip select configurations should be
reviewed with some detail. Information to configure the chip selects and memory is detailed in the following sections.
Memory Bank Chip Select Configuration
Application software that executes on reset must configure each memory bank chip select properly for correct operation. Following
is a reference table of Memory Bank chip select values:
Memory Bank
Reg. Default Value
Notes
MEM Sockets - 16 bit port
BR0
0x00400803
Base address = 0x400000, Port width = 16 bit *Default
MEM Sockets - 8-bit port
BRO
0x00400403
Port width = 8 bit
MEM Sockets
OR0
0xFFC00020
Memory Range = 0x400000, wait state = 2, 40MHz / 70ns devices
RAM – 32 bit port only
BRx
0x00800003
Base Address = 0x800000, Port width = 32 bit FIXED *Default
RAM – asynchronous mode
ORx
0xFFC0000
Memory Range = 0x400000, wait state = 0 or 1, Note:
asynchronous operation requires 1 wait state no matter clock
frequency on rev. C (CY1339 devices).
RAM – burst mode
ORx
TBD
TBD
Flash – 32 bit port asynchronous
BRx
0x00C00003
Base address 0xC00000, Port width 32 bit, *Default MAP_SW-8 =
off
Flash – 16 bit port asynchronous
BRx
0x00C00803
Base address 0xC00000, Port width = 16 bit , MAP_SW-8 = on
Flash – 32 bit port asynchronous
ORx
0xFFC00030
Memory range = 0x400000, wait state = 3, asynchronous operation
40Mhz clock, 95ns device
Flash – 32 bit port burst mode
Flash – 16 bit port burst mode
PRU – 32 bit asynchronous only
BRx
0x01000007
Base address = 0x1000000, Port width = 32 bit *Default
PRU – External terminate
ORx
0xFFFF80F0
Memory Range 0x8000, wait state = External Terminate (TA*)
*Default
MAP_SW – Ram Bank and Flash Bank Options
The MAP Switch provides chip select to memory bank selection for the Synchronous RAM Memory Bank and the Burstable Flash
Memory Bank. Positions 1-4 set the Chip Select for RAM, the rest are for Flash. Position 8 determines the Flash Bank Port Size so
that either 16 or 32 bit burstable port can be selected. If switches 1 to 7 are all off the RAM and Flash Banks are disabled.
The Default positions shown below will set RAM to CS1 and FLASH to 32 bit mode on CS2.
MAP_SW
Position
Chip
Select
Default
Position
Memory Bank Connection and Notes
1
CS0
Off
RAM – on for BDM use typically (with MEM_EN off)
2
CS1
ON
RAM –
*Default
monitor operation position
3
CS2
Off
RAM
4
CS3
Off
RAM
5
CS0
Off
Flash – on to Reset (BOOT) from Flash Bank (with MEM_EN off)
6
CS1
Off
Flash
7
CS2
ON
Flash -
*D
efault
monitor operation position
8
Flash
Port
Width
Off
Flash – Port Width
Off = 32 bit wide port (parallel flash devices),
On = 16 bit wide port (single flash device)
