BIOS SETUP
34
TL-EMBSBC 795 User’s Manual
Advanced Chipset Features
This Setup menu controls the configuration of the chipset.
Phoenix - AwardBIOS CMOS Setup Utility
Advanced Chipset Features
DRAM Timing By SPD
Enabled
ITEM HELP
Memory Hole
Disabled
Menu Level
P2C/C2P Concurrency
Enabled
System BIOS Cacheable
Disabled
Video BIOS Cacheable
Disabled
Frame Buffer Size
8M
AGP Aperture Size
64M
AGP-4X Mode
Enabled
AGP Driving Control
Auto
Panel Type
07
Boot Device Select
Both
OnChip USB
Enabled
USB Keyboard Support
Disabled
OnChip Sound
Enabled
CPU to PCI Write Buffer
Enabled
PCI Dynamic Bursting
Enabled
PCI Master 0 WS Write
Enabled
PCI#2 Access #1 Retry
Enabled
PCI Delay Transaction
Disabled
AGP Master 1 WS Write
Disabled
AGP Master 1 WS Read
Disabled
DRAM Timing by SPD
This field enables or disables the DRAM Timing based on SPD.
Memory Hole
It is recommended to leave as disabled, although enabling 15M-16M
can help with sound issues.
P2C / C2P Concurrency
Set to Disabled for best performance. You may set this to Enabled if
you want any sort of system stability.
System BIOS Cacheable
The setting of
Enabled
allows caching of the system BIOS ROM at
F000h-FFFFFh, resulting in better system performance. However, if
any program writes to this memory area, a system error may result.
Video BIOS Cacheable
The Setting
Enabled
allows caching of the video BIOS ROM at
C0000h-F7FFFh, resulting in better video performance. However, if
any program writes to this memory area, a system error may result.
Summary of Contents for TL-EMBSBC 795
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