Award TL-EMBSBC 795, User Manual

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BIOS SETUP
36 TL-EMBSBC 795 User’s Manual
OnChip Keyboard Support
Enable this if you are using a USB keyboard.
OnChip Sound
This field enables or disables the on board audio function.
CPU to PCI Write Buffer
This controls the CPU write buffer to the PCI bus. If this buffer is
disabled, the CPU writes directly to the PCI bus. The default setting is
Enabled .
PCI Dynamic Bursting
This option controls the PCI write buffer. If this is enabled, then every
write transaction on the PCI bus goes straight to the write buffer. Burst
transactions are then sent on their way as soon as there are enough to
send in a single burst.
PCI Master 0 WS Write
This function determines whether there's a delay before any writes to
the PCI bus. If this is enabled, then writes to the PCI bus are executed
immediately (with zero wait states), as soon as the PCI bus is ready to
receive data. But if it is disabled, then every write transaction to the
PCI bus is delayed by one wait state. It's recommended to enable this
for faster PCI performance.
PCI#2 Access #1 Retry
This BIOS feature is linked to the CPU to PCI Write Buffer. Normally,
the CPU to PCI Write Buffer is enabled. All writes to the PCI bus are,
as such, immediately written into the buffer, instead of the PCI bus.
This frees up the CPU from waiting till the PCI bus is free. The data are
then written to the PCI bus when the next PCI bus cycle starts.
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support
delay transactions cycles. Select
Enabled to support compliance with
PCI specification version 2.1.
AGP Master 1 WS Write/Read
When enabled a single wait state is used when writing/reading to the
AGP bus. When disabled a 2 wait state is used. For optimal
performance set this to enabled. For improved stability set it to
disabled.