26
J P 1
1
2
Edge of board
2 3
2 4
P 3
8
1 5
1
9
Figure 3 Diagram of JP1 (board revision “G”)
AVT-718 Signal
JP1 pin #
JP1 pin #
P3 pin #
VPW bus
1
shunt
2
2
PWM bus +
3
shunt
4
2
PWM bus -
5
shunt
6
10
K-line
7
shunt
8
7
L-line
9
shunt
10
15
CAN - H
11
shunt
12
6
CAN - L
13
shunt
14
14
SWC
15
16
9
UBP / LIN
17
18
3
P3 pin #1
19
20
8
P3 pin #11
21
22
12
Power to K-line, UBP,
LIN transceivers
23
shunt
24
protected
V-Batt
Table 2 Default Configuration of JP1 (board revision “G”)
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