24
A diagram of JP1 is shown in Figure 3.
The default configuration for JP1 is the first 7 pin pairs and the last pin pair are shunted.
The default configuration is shown in Table 2.
Refer to the AVT-718 unit block diagram, Figure 1. Included on the block diagram are all signal
assignments and pin numbers for JP1 and P3.
JP1 pins #23 and #24 control selection of the “V-Batt” source to the KWP, UBP, and LIN
network pull-up resistors (K-lines). By removing this shunt and then installing a wire
(wire wrap, 30 AWG) the user can provide an external or alternate source of power for the
network pull-up resistors that is separate from the power source to the AVT-718 unit.
6.3.2.3 AVT-718 PC board revision level “AA”
The routing and location of the SWC (Single Wire CAN) signal through JP1 to P3 was moved.
Jumper block JP1 is a 24-pin header that permits assignment of signals to the pins of P3, the
“Network” connector.
JP1 is numbered such that all odd numbered pins are in one row and all even numbered pins are
in the other row.
A diagram of JP1 is shown in Figure 3.
The default configuration for JP1 is the first 7 pin pairs and the last pin pair are shunted.
The default configuration is shown in Table 3.
Refer to the AVT-718 unit block diagram, Figure 1. Included on the block diagram are all signal
assignments and pin numbers for JP1 and P3.
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
