-|Transparent Guide|-
Input / Output Connections
■ When operation load by
sensor power
■ When operating load by
external power
8 9 10 11 12 13 14
1 2 3 4 5 6 7
Load1
CP1
CP2
12 VDCᜡ
N.O. N.C.
SOURCE
Load2
Power for operating load
Sensor
0 VDCᜡ
8 9 10 11 12 13 14
1 2 3 4 5 6 7
Load1
CP1
N.O.
CP2
N.C.
12 VDCᜡ
SOURCE
Constant - voltage
circuit
-
+
0 VDCᜡ
Load2
Power for operating load
The sum of operating current capacity of
load1 and sensor should not be over external
power capacity (50 mA).
The capacity of load1 should not be over
transistor switching capacity (≤ 30 VDCᜡ 100
mA)
Do not supply the reverse polarity power.
When using inductive load (relay, etc.),
connector surge absorber at both ends of the
load1.
■ How to count by external power supply
8 9 10 11 12 13 14
FX4M
Limit switch
contact
CP1 CP2
External
power supply
-
+
12 VDCᜡ
0 VDCᜡ
This unit starts to count when [H] 5 - 30 VDCᜡ is applied at CP1 or CP2 after selecting PNP. ([L]:
0 - 2 VDCᜡ)
■ Using 2 counters with one sensor
FX4H
FX6M-I
8 9 10 11 12 13 14
Black
Brown
Blue
8 9 10 11 12 13 14
Black
Blue
CP1
CP1
CP2
CP2
12 VDCᜡ
0 VDCᜡ
12 VDCᜡ 0 VDCᜡ
Sensor
Please connect as the power of sensor is supplied from only one of counters and design input
logic with same way.
Mode
Counting chart
01)
Voltage input (PNP)
No-voltage input (NPN)
Up / Down -
A
: command
input
Counting
CP1
CP2
H
H
0 1
1
2
2
2
3
3
L
L
A
A
Counting
CP1
CP2
H
H
0 1
1
2
2
2
3
3
L
L
A
A
Up / Down -
B
: individual
input
Counting
CP1
CP2
H
H
0 1
1 1
2
2
2
3
3
L
L
Counting
CP1
CP2
H
H
0
1
1 1
2
2
2
3
3
L
L
Up / Down -
C
: phase
difference
input
Counting
CP1
CP2
H
H
0
1
1
2
2
2
3
3
L
L
4-B
Counting
CP1
CP2
H
H
0 1
1
2
2
2
3
3
L
L
4-B
Up
: count up
input
Counting
CP1
CP2
H
H
0 1
2
3
No counting
4 5
L
L
A
A
Counting
CP1
CP2
H
H
0 1
2
3
No counting
4 5
L
L
A
A
Counting
CP1
CP2
H
H
0 1
2
3
No counting
4 5
L
L
A
A
Counting
CP1
CP2
H
H
0 1
2
3
No counting
4 5
L
L
A
A
Up / Down -
D
: command
input
Counting
CP1
CP2
H
H
n-1
n-1
n
n-2
n-2
n-2
n-3
n-3
0
L
L
A
A
Counting
CP1
CP2
H
H
n-1
n-1
n
n-2
n-2
n-2
n-3
n-3
0
L
L
A
A
Up / Down -
E
: individual
input
Counting
CP1
CP2
H
H
n-1
n-1 n-1
n
n-2
n-2
n-2
n-3
n-3
0
L
L
Counting
CP1
CP2
H
H
n-1
n-1 n-1
n
n-2
n-2
n-2
n-3
n-3
0
L
L
Up / Down -
F
: phase
difference
input
Counting
CP1
CP2
H
H
n-1
n-1
n
n-2
n-2
n-2
n-3
n-3
0
L
L
4-B
Counting
CP1
CP2
H
H
n-1
n-1
n
n-2
n-2
n-2
n-3
n-3
0
L
L
4-B
Down
: count down
input
Counting
CP1
CP2
H
H
n-1
n
n-2
n-3
n-4 n-5
0
No counting
L
L
A
A
Counting
CP1
CP2
H
H
n-1
n
n-2
n-3
n-4n-5
0
No counting
L
L
A
A
Counting
CP1
CP2
H
H
n-1
n
n-2
n-3 n-4 n-5
0
No counting
L
L
A
A
Counting
CP1
CP2
H
H
n-1
n
n-2
n-3 n-4 n-5
0
No counting
L
L
A
A
01) CP: clock pulse, n: +max. display value
A should be over min. signal width, B is over 1 / 2 of min. signal width. If the signal is smaller than these widths,
it may cause counting error (± 1).
Counter Operation
■ Input operation mode
