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AS354

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18h-6 AVDD27

PRG_AVDD27

VSEL_AVDD27<3:0>

0x0 – 0x2: 2.3V
0x3 – 0xF: 2.0V + VSEL* 100mV ->(2.3V – 3.5V)

18h-7 AVDD17

AVDD17_OFF

PRG_AVDD17

VSEL_AVDD17<4:0>

0x00 – 0x1F: 1.65V + VSEL * 50mV -> (1.65V – 3.2V)

19h-1 CHGVBUS1

BAT_TEMP_OF
F

CHG_I<2:0>

0..3: 55, 70, 140, 210mA
4..7: 280, 350, 420, 460mA

CHG_V<2:0>

3.9V + CHG_V * 50mV -> (3.9V – 4.25V)

CHG_OFF

19h-2 CHGVBUS2

VBUS_COMP_TH <1:0>

0: 4.5V; 1: 3.18V;
2: 1.5V; 3: 0.6V

BAT_TEMP

0: 0.4/0.5V;
1: 0.6/0.7V

CHG_EOC_TH<1:0>

0: 10% CC; 1: 30% CC;
2: 50% CC; 3: 70% CC

1Ah-1 Out_Cntr1

DRIVE_PWGD<1:0>

0: 6mA OD; 1: 6mA PP;
2: 1mA PP; 3: HiZ

MUX_PWGD<1:0>

0: PWGD; 1: -;
2: CLKINT2; 3: PWM

DRIVE_XRES<1:0>

0: 6mA OD; 1: 6mA PP;
2: 1mA PP; 3: HiZ

MUX_XRES<1:0>

0: XRES; 1: -;
2: CLKINT1; 3: PWM

1Ah-2 reserved

1Ah-3 Out_Cntr3

DRIVE_SDO<1:0>

0: 6mA PP; 1: HiZ;
2: 2mA PP; 3: 1mA PP

MUX_SDO<1:0>

0: SDO; 1: -;
2: CLKINT1; 3: PWM

DRIVE_XIRQ<1:0>

0: 6mA OD; 1: 6mA PP;
2: 1mA PP; 3: HiZ

MUX_XIRQ<1:0>

0: XIRQ; 1: CLKINT1;
2: CLKINT2; 3: IRQ

1Ah-4 In_Cntr

MUX_HBT<1:0>

0: OFF; 1: PWGD;
2: -; 3: -

MUX_ExtDim<1:0>

0: OFF; 1: PWGD;
2: -; -

1Ah-5 Clk_Cntr

CLKINT2<1:0>

0: CLKPLL; 1: CLKlogdim;
2: LOW; 3: HIGH

CLKINT1<1:0>

0: 2MHz; 1: 667kHz;
2: 1kHz; 3: 125Hz

CLK24M<1:0>

0: -; 1: -;
2: -; 3: OSC24M_PD

1Ah-6 PWM_Cntr

PWM_INVERT

PWM_CYCLE<6:0>

0: no pulses;
1-127: duty cycle = PWM_CYCLE * 0.39%

1Ah-7 PLL

OSR<3:0>

0x0: 128;
0x1-0xF: n/a

VCO_MODE<1:0>

0: 24-48kHz;
1: 8-23kHz ;
2: n/a;
3: n/a

PLL_MODE<1:0>

0: automatic;
1: ON;
2: OFF;
3: auto_inv

1Bh-1 DCDC15

DIM_UP_XDO
WN

DIM_RATE<1:0>

0: 0ms; 1: 300ms;
2: 600ms; 3: 1200ms

VFB_ON

ExtDim_ON

1Bh-2 ISINK1

I_SINK1<4:0>

0: OFF;
1-31: 1.2mA *I;_ISINK1 -> (1.2mA...37.2mA)

1Bh-3 reserved

Table 42. I2C Register Overview

Addr

Name

Summary of Contents for AS3542

Page 1: ...n internal voltage pro tection is limiting the output voltage in the case of external component failures An automatic dimming function allows a logarithmic on off of the backlight with selectable timing AS3542 also contains a Li Ion battery charger with con stant current constant voltage and trickle charging The maximum charging current is 460mA An integrated bat tery switch is separating the batt...

Page 2: ...backlight 15V current control mode 1 2 36mA voltage control mode 1 HV current sink automatic dimming over voltage protection Battery Charger automatic trickle charge 55mA prog constant current charging 55 460mA prog constant voltage charging 3 9V 4 25V current limitation for USB mode integrated battery switch General Supervisor automatic battery monitoring with interrupt genera tion and selectable...

Page 3: ...www austriamicrosystems com Revision 1 10 3 86 AS3542 3v2 Data Sheet Strictly Confidential Applications Figure 1 Block Diagram ...

Page 4: ...ut 19 8 5 DAC ADC and I2S Digital Audio Interface 22 8 6 Audio Output Mixer 25 8 7 2 Wire Serial Control Interface 26 9 Detailed Description Power Management Functions 29 9 1 Low Drop Out Regulators 29 9 2 DCDC Step Down Converter 2x 32 9 3 15V Step Up DCDC Converter 36 9 4 Charger 38 9 5 Battery Switch 41 10 Detailed Description SYSTEM Functions 42 10 1 SYSTEM 42 10 2 Hibernation 44 10 3 Supervis...

Page 5: ...sion 1 10 5 86 AS3542 3v2 Data Sheet Strictly Confidential Applications Revision History Table 1 Revision History Revision Date Owner Description 1 00 17 4 2009 pkm official release 1 10 26 5 2009 pkm added audio characterisation data ...

Page 6: ...UP IN Li Ion Charger Input 4 BATTEMP ANA IO Li Ion Charger Battery Temp Sensor Input 5 VSS GND Power Management Neg Reference Supply 6 SW15V DIG OUT DCDC15V Switch Output to Coil 7 VSSPWR GND Power Management Neg Supply Terminal 8 ISINK ANA IO DCDC15V Load Current Sink Terminal 9 BVDDC2 SUP IN CVDD2 Step Down Pos Supply Terminal 10 LXC2 DIG OUT CVDD2 Step Down Switch Output to Coil 11 CVDD2 ANA IN...

Page 7: ...s Supply 33 VREF ANA IO DAC Reference Pin 34 VPRG2 ANA IN Memory Supply Voltage Definition Pin 35 VPRG3 ANA IN PowerUp Sequence Definition Pin 36 AVSS GND Ground analog 37 AGND ANA IO Analog Common Mode Voltage Pin 38 MICP ANA IN Microphone Input 39 MICS ANA IO Microphone Supply Output Remote Control input 40 LOGND ANA IO Line Output Common Mode Voltage Pin 41 LIOR ANA IO Analog Line Input 1 Right...

Page 8: ...trictly Confidential Pinout 53 PVDD2 ANA OUT LDO4 Output PVDD2 54 PVDD1 ANA OUT LDO3 Output PVDD1 55 BVDDP1 SUP IN LDO3 Pos Supply Terminal 56 CHGOUT SUP IO Li Ion Charger Output battery switch input Table 2 Pin Description for AS3542 Pin Number Pin Name Type Description ...

Page 9: ... terminals 0 5 0 5 V Applicable for pins VSS VSS15V CVSS12 HPVSS AVSS DVSS 3 3V pins with protection to AVDD27 0 5 5 0 AVDD27 V Applicable for pins BATTEMP HPGND 3 3V pins with protection to DVDD 0 5 5 0 DVDD 0 5 V Applicable for pins MCLK LRCK SCLK SDI SDO XIRQ XRES PWGD 3 3V pins with protection to AVDD17 0 5 5 0 AVDD17 0 5 V Applicable for pins LIOL R LOGND VREF AGND MICP MICS 3 3V pins with pr...

Page 10: ...tings Bump Temperature soldering Package Body Temperature 260 C Norm IPC JEDEC J STD 020C reflects moisture sensitivity level only Moisture Sensitive Level 3 1 Represents a max floor live time of 168h 1 Depending on actual PCB layout and PCB used Table 3 Absolute Maximum Ratings Parameter Min Max Units Comments ...

Page 11: ...Voltage 1 7 1 7 3 5 V AGND Analog Ground Voltage Internally generated AVDD17 2 V VDELTA Difference of Negative Supplies CVSS12 VSS15V HPVSS AVSS DVSS VSS To achieve good performance the negative supply terminals should be connected to low impedance ground plane 0 1 0 1 V VDELTA Difference of Positive Supplies RVDD AVDD27 AVDD17 AVDD27 FVDD AVDD27 0 V HPVDD AVDD27 0 3 V AVDD27 BVDD 0 1 V POR Watchd...

Page 12: ...regulators off only LDO2 on 210 uA IBIAS Audio Bias current 32 uA ISUM Summing stage current 174 uA ILIN Line input stage current no signal 146 uA IMIC Mic input stage current no signal 643 uA IMICS Mic Supply stage current no load 201 uA ILOUT Line output stage current no load 436 uA IDAC_GS DAC gain stage current no signal 214 uA IADC_GS ADC gain stage current no signal 1 36 mA IHPH Headphone st...

Page 13: ... 0 560 VRMS RL 16Ω 0 550 VRMS SNR Signal to Noise Ratio A weighted no load silence input 97 dB DR Dynamic Range A weighted no load 60dB FS f 1kHz 94 dB THD Total Harmonic Distortion no load f 1kHz FS input 87 dB POUT 6mW RL 32Ω f 1kHz 1dB FS 81 dB POUT 12mW RL 16Ω f 1kHz 1dB FS 78 60 dB CS Channel Separation RL 32Ω 63 dB RL 16Ω 60 dB Line Input to HP Output FS Full Scale Output RL 32Ω f 1kHz 545mV...

Page 14: ...w austriamicrosystems com Revision 1 10 14 86 AS3542 3v2 Data Sheet Strictly Confidential Typical Operating Characteristics 7 Typical Operating Characteristics BVDD 3 6V TA 25ºC unless otherwise specified ...

Page 15: ... the volume and mute control can only be done after enabling the input Line Input and Line Output are sharing the same pins Please make sure to disable the line out discharge resistors when using line input LO_DISCHG_OFF in reg 0Bh Figure 3 Line Inputs 8 1 2 Parameter AVDD17 1 7V AVDD27 2 7V TA 25 o C unless otherwise mentioned Table 6 Line Input Parameter Symbol Parameter Condition Min Typ Max Un...

Page 16: ...ied with 32 1 5dB pro grammable logarithmic gain steps and MUTE All gains and MUTE are independently programmable The gain can be set from 40 5dB to 6dB The stage features a soft start function Pre amplifier and gain stage settings can be set before enabling the micro phone stage After enabling the stage to gain is automatically set to the defined value by using the 128 steps of the AGC 8 2 3 Supp...

Page 17: ...ameter Symbol Parameter Condition Min Typ Max Unit VMICIN0 Input Signal Level AMICPRE 30dB AMIC 0dB 20 mVP VMICIN1 AMICPRE 36dB AMIC 0dB 10 mVP VMICIN2 AMICPRE 42dB AMIC 0dB 5 mVP RMICIN Input Impedance MICP to AGND 7 5 kΩ ΔMICIN Input Impedance Tolerance 7 33 CMICIN Input Capacitance 5 pF AMICPRE Microphone Preamplifier Gain Preamplifier has 3 selectable fixed gain settings 30 36 42 dB AMIC Progr...

Page 18: ... Changing the input multiplexer from one source to another will be done by fadeing out to mute source changing and fading in of the new source to the target volume Change from HPH out to LINE out is done by fading out of HPH out to mute and fading in of the LINE out to the target volume The fading speed can be programmed to 3 different speed levels The immediate response can be selected as 4th sta...

Page 19: ...h 32 steps 1 5dB each The gain can be set from 40 5dB to 6dB Figure 6 Headphone Output Table 10 Line Output Parameter Symbol Parameter Condition Min Typ Max Unit RL_LO Load Impedance Stereo Mode line inputs nominally have 10kΩ 5 kΩ CL_LO Load Capacitance Stereo Mode 100 pF ALO Programmable Gain 40 5 6 dB Gain Steps discrete logarithmic gain steps 1 5 dB Gain Step Accuracy 0 25 dB ALOMUTE Mute Atte...

Page 20: ...ins HPR HPL is incorporated into the AFE The 470nF capacitor at pin HPGND is used to form the charge discharge slope Pls observe that pin HPGND is a high impedance node which must not be connected to any other external device than the 470nF buffer capacitor To avoid Pop Click noise one has to wait for 750ms in between a power down switch off and a power up switch on of the headphone amplifier 8 4 ...

Page 21: ... out period 512ms 0ms There is a corresponding interrupt available to be enabled Figure 10 Headphone Overcurrent OFF ON Sequence 8 4 6 Ground Noise Cancelation As separate ground input allows to connect a ground sense line direct from the dock connector ground or headphone jack shield to make the audio output independent from PCB ground noise 8 4 7 Power Options To save power especially when drivi...

Page 22: ...udio channels multiplexed into one bit stream Via pin LRCK the alignment clock is signalled to the connected devices e g CPU LRCLK Left Right Clock indicates whether the serial bit stream sent via pin SDI presents right channel or left channel audio data Via pin SCLK the bit clock for the serial bit stream is sig nalled SDO and LRCK are synchronous with SCLK SDO is an output LRCK and SCK are input...

Page 23: ...put changes A bit in the interrupt register represents the actual state present or not present of the LRCK 8 5 5 Signal Description The digital audio interface uses the standard I2S format left justified MSB first one additional leading bit The on chip synchronization circuit allows any bit count up 32bit When there are less than 18 bits sampled the data sample is completed with 0 s In I2S direct ...

Page 24: ...0 ns TLRSU LRCK Setup Time before SCLK rising edge 80 ns TLRHD LRCK Hold Time after SCLK rising edge 80 ns tSDSU SDI setup time before SCLK rising edge 25 ns tSDHD SDI hold time after SCLK rising edge 25 ns tSDOD SDO Delay from SCLK falling edge 25 ns tJITTER Jitter of LRCK internal PLL generates MCLK from LRCK 20 20 ns I2S direct mode TSCD SCLK delay after MCLK rising edge 0 5 1 5 ns TLRD LRLCK d...

Page 25: ...automatic gain control AGC which automatically avoids clipping 8 6 2 Register Description Table 15 Audio Converter Related Register Name Base Offset Description DAC_R 2 wire serial 0Eh DAC input volume settings DAC_L 2 wire serial 0Fh DAC input volume settings ADC_R 2 wire serial 10h ADC output volume settings source multiplexer settings ADC_L 2 wire serial 11h ADC output volume settings sampling ...

Page 26: ...E state the bus is free The device write address is followed by the word address After the word address any number of data bytes can be sent to the slave The word address is incremented internally in order to write subsequent data bytes on subsequent address locations Table 17 2 Wire Serial Symbol Definition Symbol Definition RW Note S Start condition after stop R 1 bit Sr Repeated start R 1 bit D...

Page 27: ...it ter In this state the slave transmits register data located by the previous received word address vector The master responds to the data byte with a not acknowledge and issues a STOP condition on the bus Figure 16 Sequential Read Sequential Read is the extended form of Random Read as more than one register data bytes are transferred subse quently In difference to the Random Read for a sequentia...

Page 28: ...V VCSH CSCL CSDA High Input Level CSCL CSDA min 70 DVDD 2 03 5 5 V HYST CSCL CSDA Input Hysteresis 200 450 800 mV VOL CSDA Low Output Level at 3mA 0 4 V Tsp Spike insensitivity 50 100 ns TH Clock high time max 400kHz clock speed 500 ns TL Clock low time max 400kHz clock speed 500 ns TSU CSDA has to change Tsetup before rising edge of CSCL 250 ns THD No hold time needed for CSDA relative to rising ...

Page 29: ...works The low impedance of the power device enables the device to deliver up to 150mA even at nearly discharged batteries without any decrease of performance Figure 19 LDO Block Diagram 9 1 2 LDO1 This LDO generates the audio supply voltage used for the AFE itself Input voltage is VDD17IN Output voltage is VDD17 typ 1 7V Driver strength 50mA It is set to a default output voltage of 1 7V 50mAmax It...

Page 30: ...o 3 5V Default value at start up is defined by VPRG2 pin Driver strength 100mA 9 1 5 Parameter BVDD 3 6V TA 25 o C unless otherwise mentioned Table 19 LDO Parameter Symbol Parameter Condition Min Typ Max Unit RON On resistance 1 Ω PSRR Power supply rejection ratio f 1kHz 70 dB f 100kHz 40 IOFF Shut down current 100 nA IVDD Supply current without load 50 μA Noise Output noise 10Hz f 100kHz 50 μVrms...

Page 31: ...ut load 10mA transient input voltage ripple 500mV output load 150mA transient input voltage ripple 500mV Table 20 LDO Related Register Name Base Offset Description PVDD1 2 wire serial 18h 1 PVDD1 LDO3 control and voltage settings PVDD2 2 wire serial 18h 2 PVDD2 LDO4 control and voltage settings AVDD27 2 wire serial 18h 6 AVDD27 LDO2 control and voltage settings AVDD17 2 wire serial 18h 7 AVDD17 LD...

Page 32: ...rength 250mA under and over voltage detection Figure 21 DCDC Step Down Block Diagram 9 2 2 Functional Description The step down converter is a high efficiency fixed frequency current mode regulator By using low resistance internal PMOS and NMOS switches efficiency up to 97 can be achieved The fast switching frequency allows using small inductors without increasing the current ripple The unique fee...

Page 33: ...d current force pulse skip mode 1 LXC1 voltage 2 coil current 1mV 1mA 3 output voltage High efficiency operation In this mode there is a minimum coil current necessary before switching off the PMOS As result fewer pulses at low output loads are necessary and therefore the efficiency at low output load is increased On the other hand the output voltage ripple increases and the noisy pulse skip opera...

Page 34: ...Ω RNSW N Switch ON resistance BVDD 3 0V 0 5 0 7 Ω fSW Switching frequency depending on DCDC_Cntr settings 1 2 MHz fSWsc Switching frequency in shortcut case 0 6 MHz Cout Output capacitor Ceramic 10 tolerance 10 μF Lx Inductor 10 tolerance 2 2 4 7 μH ηeff Efficiency Iout 100mA Vout 3 0V 97 IVDD Current consumption Operating current without load Low power mode current Shutdown current 220 100 0 1 μA...

Page 35: ...al 17h 2 CVDD2 DCDC2 voltage settings Hibernation 2 wire serial 17h 6 Hibernation control DCDC_Cntr 2 wire serial 17h 7 DCDC frequency and DVM settings PMU_Enable 2 wire serial 1Ch Enables writings to extended registers 17h 1 to 17h 7 Output voltage vs Output Current 1 175 1 185 1 195 1 205 1 215 1 225 0 50 100 150 200 250 OUTPUT CURRENT mA OUTPUT VOLTAGE V VIN 3 6V Line Regulation 1 195 1 2 1 205...

Page 36: ...be used to avoid an exceeding of the operation conditions in a no load situation 9 3 2 Dimming The DCDC boster together with the current sinks has an adjustable automatic logarithmic dimming for a smooth ON OFF transition It is also possible to control the dimming with an external signal via a GPIO pin PWGD Q24M or Q32K pin can be selected as input for the external dimming signal 9 3 3 Current Sin...

Page 37: ...P Pulse skip Threshold Voltage at pin ISINK pulse skips are introduces when load current becomes too low 0 96 V FIN Fixed Switching Frequency 0 45 0 66 0 85 MHz COUT Output Capacitor Ceramic 1 µF L Inductor ILOAD 20mA Use inductors with small CPARASITIC 100pF for high efficiency 17 22 27 µH ILOAD 20mA 8 10 27 tMIN_ON Minimum On Time Guaranteed per design 90 200 ns MDC Maximum Duty Cycle Guaranteed...

Page 38: ...ng current when a CHGIN voltage drop is detected For the end of charge current four levels can be selected while the battery temperature shutdown has two temperature levels to choose from The current battery voltage as well as the actual charging current can be measured with the general purpose ADC Figure 27 Charger Block Diagram Table 24 DCDC15 Related Register Name Base Offset Description In_Cnt...

Page 39: ...bits at any time 9 4 4 Temperature Supervision This charger block also features a 15uA supply for an external 100k NTC resistor to measure the battery temperature while charging If the temperature is too high an interrupt can be generated If the battery temperature drops the char ger will start charging again The levels for switching off on the charger 45 42 C or 55 50 C can be selected via reg is...

Page 40: ...uA Table 26 Charger Related Register Name Base Offset Description CHGVBUS1 2 wire serial 19h 1h Charger voltage current and temp supervision control CHGVBUS2 2 wire serial 19h 2h Charger temperature and EOC level settings PMU_Enable 2 wire serial 1Ch Enables writings to extended registers 19h 1 to 19h 2 IRQENRD_2 2 wire serial 25h Enable disable EOC and battery over temperature interrupt Read out ...

Page 41: ...ion Power Management Functions 9 5 Battery Switch 9 5 1 General An integrated battery switch provides a battery separation during charging In normal battery operation the switch is closed With an ideal diode function a smooth transition between the different modes are guaranteed Figure 29 Battery Switch Modes ...

Page 42: ...y PwDn Power Down if PWRUP pin is HIGH for 10sec This time can be reduced to 5sec with bit 7 in register 21h 3 Wake Up PwDn write 4h to reg 1Ch and 0h to reg 1Ah disable heartbeat source Write 3 times to reg 22h to define wake up time Power Down by heartbeat without source by writing 9h to reg 20h 4 Heartbeat PwDn write 4h to reg 1Ch and 4h 8h or Ch to reg 1Ah select HBT source write 9h to reg 20h...

Page 43: ...for the internal supply of the AFE LDO1 could be turned off later if no audio functionality is needed After power up sequence all voltage settings and power on off conditions of the described regulators can be pro grammed via the serial interface 10 1 4 XRES delay with PWGD pin With using an exteral capacitor on PWGD the XRES signal can be delayed This delay can be calculated with the 10uA pull up...

Page 44: ...rger USB and supervisor interrupts IRQENRD_3 2 wire serial 26h Enable disable junction temperature interrupt Table 31 Hibernation State Description Enter To enter hibernation mode the following settings have to be done Enable just these IRQ sources which should lead to leave hibernation mode Make sure that IRQ is inactive IRQ flags get cleared by Reg0x23 27 readings Define which regulators should ...

Page 45: ...ster Description 10 4 Interrupt Generation 10 4 1 General All interrupt sources can get enabled or disabled by corresponding bits in the 5 IRQ bytes By default no interrupt source is enabled The XIRQ output can be configured to operate in push pull 2 different driver strengths open drain mode or to be tri state The signal polarity can be defined as active low or active high Default state is open d...

Page 46: ...ct Charger changed end of charge or connect disconnect Battery temperature high at 45ºC or 55ºC with 100kΩ NTC Junction temperature high RTC watchdog e g after battery was changed Battery low Brown out voltage reached Wake up from hibernation Power up key pin PWRUP pressed Power rail monitor over voltage PVDD1 PVDD2 CVDD1 CVDD2 DCDC15 Power rail monitor under voltage PVDD1 PVDD2 CVDD1 CVDD2 AVDD27...

Page 47: ...s Source Range LSB Description 0 BVDD 5 120V 5mV check main system input voltage 1 reserved 2 CHGIN 5 120V 5mV check charger input voltage 3 CHGOUT 5 120V 5mV check battery voltage of 4V Li Ion accumulator 4 VBUS 5 120V 5mV check USB input voltage 5 5 120V 5mV Source defined by DC_TEST in register 18h 6 BatTemp 2 048V 2mV check battery charging temperature 7 reserved 8 MICS 2 048V 2mV check voltag...

Page 48: ...cies of 125Hz 1kHz 667kHz or 2MHz This signal line can be selected as source for the XRES XIRQ and SDO GPIO output pins CLKINT2 Signal This is an internal signal line which can drive the PLL clock the clock for the logarithmic dimming of DCDC15 or can be set to static HIGH LOW This signal line can be selected as source for the PWGD and XIRQ output pins PWM Signal The duty cycle of the PWM signal c...

Page 49: ...ion 10 8 12 24MHz Oscillator 10 8 1 General This oscillator is not available in this package As the oscillator is default ON it has to be disabled 10 8 2 Register Description 10 9 Unique ID Code 64 bit OTP ROM 10 9 1 General This fuse array is used to store a unique identification number which can be used for DRM issues The number is gen erated and programmed during the production process 10 9 2 R...

Page 50: ...dB 3 reserved MICR_VOL 4 0 Gain from MicAmp N4 to Mixer N12 40 5dB 6dB 07h MIC_L MSUP_OFF MUTE_D_ON MICL_VOL 4 0 Gain from MicAmp N4 to Mixer N13 40 5dB 6dB 08h reserved 09h reserved 0Ah LINE_IN_R MUTE_B_OFF LIR_VOL 4 0 Gain from MUX_E N27 to Mixer N10 40 5dB 6dB 0Bh LINE_IN_L LO_DISCHG_O FF LI_MODE 0 stereo 1 mono MUTE_G_OFF LIL_VOL 4 0 Gain from MUX_E N28 to Mixer N17 40 5dB 6dB 0Ch reserved 0Dh...

Page 51: ...2 650V 3 350V 17h 2 CVDD2 PROG_CVDD2 VSEL_CVDD2 6 0 0 OFF 0x01 0x40 0 6V VSEL 12 5mV 0 6125V 1 400V 0x41 0x70 1 4V VSEL 0x40 25mV 1 425V 2 600V 0x71 0x7F 2 6V VSEL 0x70 50mV 2 650V 3 350V 17h 3 reserved 17h 4 reserved 17h 5 reserved 17h 6 Hibernation KEEP_PVDD2 KEEP_PVDD1 KEEP_CVDD2 KEEP_CVDD1 17h 7 DCDC_Cntr CVDD2_fast 0 Cext 10uF 1 Cext 22uF CVDD1_fast 0 Cext 10uF 1 Cext 22uF CVDD2_freq 0 2MHz 1...

Page 52: ... PP 3 HiZ MUX_XRES 1 0 0 XRES 1 2 CLKINT1 3 PWM 1Ah 2 reserved 1Ah 3 Out_Cntr3 DRIVE_SDO 1 0 0 6mA PP 1 HiZ 2 2mA PP 3 1mA PP MUX_SDO 1 0 0 SDO 1 2 CLKINT1 3 PWM DRIVE_XIRQ 1 0 0 6mA OD 1 6mA PP 2 1mA PP 3 HiZ MUX_XIRQ 1 0 0 XIRQ 1 CLKINT1 2 CLKINT2 3 IRQ 1Ah 4 In_Cntr MUX_HBT 1 0 0 OFF 1 PWGD 2 3 MUX_ExtDim 1 0 0 OFF 1 PWGD 2 1Ah 5 Clk_Cntr CLKINT2 1 0 0 CLKPLL 1 CLKlogdim 2 LOW 3 HIGH CLKINT1 1 ...

Page 53: ...2_IRQ PVDD1_SD PVDD1_IRQ CVDD1_under CVDD1_over PVDD2_under PVDD2_over PVDD1_under PVDD1_over 24h IRQENRD_1 PWRUP_IRQ WAKEUP_IRQ MCLK_IRQ CVDD2_SD CVDD2_IRQ CVDD2_under CVDD2_over 25h IRQENRD_2 BATTEMP_IRQ CHG_IRQ USB_IRQ RTC_WD BVDD_LOW CHG_EOC CHG_CON CHG_changed USB_CON USB_changed 26h IRQENRD_3 JTEMP_HIGH HP_OVC I2S_IRQ VOXM_IRQ MIC_CON HPH_CON I2S_status I2S_changed 27h IRQENRD_4 T_DEB 1 0 0 ...

Page 54: ...ly Confidential R e g i s t e r D e f i n i t i o n UID Register 38h UID_0 ID 7 0 39h UID_1 ID 15 8 3Ah UID_2 ID 23 16 3Bh UID_3 ID 31 24 3Ch UID_4 ID 39 32 3Dh UID_5 ID 47 40 3Eh UID_6 ID 55 48 3Fh UID_7 ID 63 56 Table 42 I2C Register Overview Addr Name b7 b6 b5 b4 b3 b2 b1 b0 ...

Page 55: ...ttings for right headphone line output adjustable in 32 steps 1 5dB gain from MUX_C to HPR LOUTR 11111 6 dB gain 11110 4 5 dB gain 00001 39 dB gain 00000 40 5 dB gain Table 44 OUT_L Register Name Base Default OUT_L 2 wire serial 00h Offset 03h Left HP Line Output Register Configures the audio gain from MUX_C output to HPL LOUTL output and controls MUTE switch K as well as on off of the stage This ...

Page 56: ...use 4 0 MICR_VOL 4 0 00000 R W volume settings for right microphone input adjustable in 32 steps 1 5dB gain from microphone amplifier N4 to mixer input N12 11111 6 dB gain 11110 4 5 dB gain 00001 39 dB gain 00000 40 5 dB gain Table 46 MIC_L Register Name Base Default MIC_L 2 wire serial 00h Offset 07h Left Microphone Input Register Configures the gain from microphone amplifier output up to mixer i...

Page 57: ... 5 dB gain 00001 39 dB gain 00000 40 5 dB gain Table 48 LINE_IN_L Register Name Base Default LINE_IN_L 2 wire serial 00h Offset 0Bh Left Line Input Register Configures the gain from analog left line input MUX E to mixer input Σ and controls MUTE switch G This register is reset when the block is disabled in AudioSet1 register 14h or at a AVDD27 POR The register cannot be written when the block is d...

Page 58: ...output N19 to mixer input N23 11111 6 dB gain 11110 4 5 dB gain 00001 39 dB gain 00000 40 5 dB gain Table 50 DAC_L Register Name Base Default DAC_L 2 wire serial 00h Offset 0Fh Left DAC Output Register Configures the gain from DAC output to mixer input Σ and controls MUTE switch H This register is reset when the block is disabled in AudioSet1 register 14h or at a AVDD27 POR The register cannot be ...

Page 59: ... A output to ADC mixer input Σ N9 11111 12 dB gain 11110 10 5 dB gain 00001 33 dB gain 00000 34 5 dB gain Table 52 ADC_L Register Name Base Default ADC_L 2 wire serial 00h Offset 0Fh Left ADC Input Register Configures the ADC mode gain from MUX_A output to the ADC mixer input Σ input and controls MUTE switch A This register is reset when the block is disabled in AudioSet1 register 14h or at a AVDD...

Page 60: ...om SDI pin to DAC input 11111 1 5 dB gain 11110 3 dB gain 00001 46 5 dB gain 00000 48 0 dB gain Table 54 AudioSet1 Register Name Base Default AudioSet1 2 wire serial 00h Offset 14h First Audio Set Register Powers the various audio inputs and outputs UP or DOWN Caution This control register resets and holds LineIn DAC and ADC related regis ters in reset After activation the required register settin...

Page 61: ...he transition time of the auto fading for the output stage 00 2ms step 01 4ms step 10 8ms step 11 auto fading off 1 0 VMICS 1 0 00 R W Sets the microphone supply output voltage 00 AVDD17 20 17 01 AVDD17 20 22 10 AVDD17 20 27 11 AVDD17 20 32 Table 56 AudioSet3 Register Name Base Default AudioSet3 2 wire serial 00h Offset 16h Third Audio Set Register Control of mixer stage inputs and headphone This ...

Page 62: ...r the DC DC converter down 00h DC DC powered down 01h 40h CVDD1 0 6V VSEL_CVDD1 12 5mV 41h 70h CVDD1 1 4V VSEL_CVDD1 25mV 71h 7Fh CVDD1 2 6V VSEL_CVDD1 50mV Table 58 CVDD2 Register Name Base Default CVDD2 2 wire serial 00h Offset 17h 2 CVDD2 DC DC Buck Regulator Control Register This is an extended register and needs to be enabled by writing 010b to Reg 1Ch first This register is reset at a AVDD27...

Page 63: ...ogrammed CVDD2 level during hibernation 0 power down CVDD2 1 keep CVDD2 0 KEEP_CVDD1 0 R W Keeps the programmed PVDD1 level during hibernation 0 power down CVDD1 1 keep CVDD1 Table 60 DCDC_Cntr Register Name Base Default DCDC_Cntr 2 wire serial 00h Offset 17h 7 DC DC Step Down Control Register This is an extended register and needs to be enabled by writing 111b to Reg 1Ch first This register is re...

Page 64: ...eg 1Ch first This register is reset at a AVDD27 POR Bit Bit Name Default Access Bit Description 7 PVDD1_OFF 0 R W Switches off PVDD1 regulator 0 normal mode 1 PVDD1 switched off 6 0 n a 5 PRG_PVDD1 0 R W Selects the output voltage control mode for PVDD1 0 PVDD1 is in default mode controlled by pin VPRG2 1 PVDD1 is register controlled Reg 18 1h 4 0 VSEL_PVDD1 4 0 00000 R W Sets the LDO output volta...

Page 65: ...2h 4 0 VSEL_PVDD2 4 0 00000 R W Sets the LDO output voltage in register control mode default voltage of the regulator is selcted by pin VPRG2 0x00 0x0F 1 2V VSEL 50mV 1 2V 1 95V 0x10 0x1F 2 0V VSEL 0x10 100mV 2 0V 3 5V Table 63 AVDD27 Register Name Base Default AVDD27 2 wire serial 00h Offset 18h 6 AVDD27 Control Register This is an extended register and needs to be enabled by writing 110b to Reg ...

Page 66: ... R W Sets the LDO output voltage in register control mode default voltage of the regulator is 1 7V 0x00 0x1F 1 65V VSEL 100mV 1 65V 3 2V Table 65 CHGVBUS1 Register Name Base Default CHGVBUS1 2 wire serial 00h Offset 19h 1 Charger VBUS 1 Control Register This is an extended register and needs to be enabled by writing 001b to Reg 1Ch first This register is reset at a AVDD27 POR Bit Bit Name Default ...

Page 67: ...with 100k NTC 1 0 CHG_EOC_TH 1 0 00 R W Setes the threshold for the charger EOC end of charge interrupt as a ratio of the constant current CC setting 00 10 CC 01 30 CC 10 50 CC 11 70 CC Table 67 Out_Cntr1 Register Name Base Default Out_Cntr1 2 wire serial 00h Offset 1Ah 1 PWGD and XRES Output Control Register This is an extended register and needs to be enabled by writing 001b to Reg 1Ch first Thi...

Page 68: ...ts various driving strengths 00 6mA push pull output 01 HiZ stri state 10 2mA push pull output 11 1mA push pull output 5 4 MUX_SDO 1 0 00 R W Multiplexes various digital signals to theSDO output pin 00 SDO serial data output of the audio ADC 01 10 CLKINT1 internal clock signal see Clk_Cntr regsiter 11 PWM PMW_Cntr register 3 2 DRIVE_XIRQ 1 0 00 R W Sets the XIRQ output pin to open drain push pull ...

Page 69: ...be set in DCDC15 register 01 PWGD pin 10 11 Table 70 Clk_Cntr Register Name Base Default Clk_Cntr 2 wire serial 00h Offset 1Ah 5 Clock Control Register This is an extended register and needs to be enabled by writing 101b to Reg 1Ch first This register is reset at a AVDD27 POR Bit Bit Name Default Access Bit Description 7 6 CLKINT2 1 0 00 R W Selects the CLKINT2 input source Note this is an interna...

Page 70: ...2 wire serial 00h Offset 1Ah 7 PLL Register This is an extended register and needs to be enabled by writing 111b to Reg 1Ch first This register is reset at a AVDD27 POR Bit Bit Name Default Access Bit Description 7 4 OSR 3 0 0000 R W Sets the oversampling rate when using the internal PLL 0x0 128 0x1 0xF n a 3 2 VCO_MODE 1 0 00 R W Selects the speed of the PLL VCO according to the audio sampling fr...

Page 71: ...nabling or disablilng the DCDC15 00 0ms 01 300ms 10 600ms 11 1200ms 4 VFB_ON 0 R W 0 current feedback selected via ISINK1 and ISINK2 1 voltage feedback selected ISINK1 is sinking 50uA to define the voltage via an external zener diode 3 ExtDim_ON 0 R W 0 selects internal clock for dimming 1 selects external clock for dimming 2 0 000 n a Table 74 ISINK1 Register Name Base Default ISINK1 2 wire seria...

Page 72: ...TEST_MUX 3 0 0000 R W Allows multiplexing internal and external supply voltages to one DC test node which can be further multiplexed to the ADC10 The accuracy is 5mV LSB see reg 2Eh 0x0 open 0x1 AVDD27 0x2 AVDD17 0x3 PVDD1 0x4 PVDD2 0x5 CVDD1 0x6 CVDD2 0x7 RVDD 0x8 FVDD 0x9 PWGD 0xA 0xF n a 3 PMU_GATE 000 R W Enables all settings made in registers 17h to 1Bh at once If this bit is set changes are ...

Page 73: ...rature supervision disabled 1 I2C_WD_ON 0 R W 2 wire serial interface watchdog To reset the watchdog counter a 2 wire serial read operation has to be performed at least every 500ms If the watchdog counter is not reset the AFE will be powered down 0 watchdog is disabled 1 watchdog is enabled 0 PWR_HOLD 0 R W 0 power up hold is cleared and AFE will power down 1 is automatically set to on after power...

Page 74: ... a 5 under voltage at CVDD1 occurs 6 CVDD1_IRQ 0 W Enables interrupt for over voltage under voltage supervision of CVDD1 0 disable 1 enable CVDD1_over x R This bit is set when a 8 over voltage at CVDD1 occurs 5 4 00 n a 3 PVDD2_SD 0 W Invokes shut down of AFE when a 10 under voltage spike at PVDD2 occurs 0 disable 1 enable PVDD2_under x R This bit is set when a 5 under voltage at PVDD2 occurs 2 PV...

Page 75: ... a high level of min BVDD 3 at the PWRUP input pin occurs PWRUP pin is commonly connected to the power up button 6 WAKEUP_IRQ 0 W Enables interrupt which is invoked whenever a wake up from RTC wake up counter occurs 0 disable 1 enable x R This bit is set when a wake up has been invoked by the RTC wake up counter 5 MCLK_IRQ 0 W Enables interrupt which is invoked whenever a high signal at the MCLK i...

Page 76: ...e turned on again when the temperature gets below 42 50 C 6 CHG_EOC x R Battery end of charge interrupt reading 0 battery charging in progress 1 charging is complete charging current is below 10 of nominal current turn off charger 5 CHG_CON x R 0 no charger input source connected 1 charger input source connected also valid if charger is connected during wakeup 4 CHG_IRQ 0 W Charger status change i...

Page 77: ...Register Please be aware that writing to this register will enable disable the corresponding interrupts while reading gets the actual interrupt status and will clear the register at the same time It is not possible to read back the interrupt enable disable settings This register is reset at a AVDD27 POR Bit Bit Name Default Access Bit Description 7 JTEMP_HIGH level 0 W Supervisor junction over tem...

Page 78: ...W Microphone connect detection interrupt setting 0 disable 1 enable x R Microphone connect detection interrupt reading 0 no microphone connected to MIC input 1 microphone connected at MIC input This interrupt is only invoked when the microphone stage is powered down The IRQ will be released after enabling the microphone stage Detecting a microphone during operation has to be done by measuring the ...

Page 79: ... 10 128ms 11 0ms 5 AVDD27_IRQ 0 W Enables interrupt for under voltage supervision of AVDD27 0 disable 1 enable AVDD27_under x R This bit is set when a 5 under voltage at AVDD27 occurs 4 DCDC15_IRQ 0 W Enables interrupt for over voltage supervision of SW15 0 disable 1 enable DCDC15_over x R This bit is set when SW15 exceeds 15V 3 0 n a 2 REM_DET edge 0 W Microphone remote key press detection interr...

Page 80: ... First 10 bit ADC Register Writing to this register will start the measurement of the selected source This register is reset at a AVDD27 POR exception are bit 0 and 1 Bit Bit Name Default Access Bit Description 7 4 ADC10_MUX 3 0 0000 R W Selects ADC input source 0000 BVDD 0001 BVDDR 0010 CHGIN 0011 CHGOUT 0100 VBUS 0101 defined by DC_TEST in register 0x1C 0110 BATTEMP 0111 reserved 1000 MICS 1001 ...

Page 81: ...a Offset 38h to 3Fh UNIQUE ID Register This is a read only register and gets not reset Adr Byte Name Default Access Bit Description 38h UID_0 n a R Unique ID byte 0 39h UID_1 n a R Unique ID byte 1 3Ah UID_2 n a R Unique ID byte 2 3Bh UID_3 n a R Unique ID byte 3 3Ch UID_4 n a R Unique ID byte 4 3Dh UID_5 n a R Unique ID byte 5 3Eh UID_6 n a R Unique ID byte 6 3Fh UID_7 n a R Unique ID byte 7 ...

Page 82: ...www austriamicrosystems com Revision 1 10 82 86 AS3542 3v2 Data Sheet Strictly Confidential Application Information 12 Application Information Figure 30 Typical Application Schematic ...

Page 83: ...10 83 86 AS3542 3v2 Data Sheet Strictly Confidential Package Drawings and Markings 13 Package Drawings and Markings Figure 31 MLF56 Marking Table 87 Package Code AYWWZZZ A Y WW ZZZ B for Green year working week assembly packaging free choice ...

Page 84: ...www austriamicrosystems com Revision 1 10 84 86 AS3542 3v2 Data Sheet Strictly Confidential Package Drawings and Markings Figure 32 MLF56 0 4mm pitch ...

Page 85: ...ta Sheet Strictly Confidential Ordering Information 14 Ordering Information Table 88 Ordering Information Model Description Delivery Form Package AS3542 EMFP Ultra Low Power Stereo Audio Codec with System PMU Tape Reel dry pack MLF2 56 7 0x7 0x0 85mm 0 4mm pitch ...

Page 86: ...n normal commercial applications Applications requiring extended temperature range unusual environmental requirements or high reliability applications such as military medical life support or life sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application For shipments of less than 100 parts the manufacturing flow might show d...

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