www.austriamicrosystems.com
Revision 1.10
24 - 86
AS3542 3v2
Data Sheet, Strictly Confidential - D e ta i l e d D e s c r i p t i o n - A u d i o F u n c t i o n s
8.5.6 Parameter
DVDD=2.9V, T
A
=25°C, Slave Mode, f
S
=48kHz, MCLK = 128*f
S,
unless otherwise specified
Table 14. I2S Timing
Symbol
Parameter
Condition
Min
Typ
Max
Unit
t
SCLK
SCLK Cycle Time
160
ns
t
SCLKH
SCLK Pulse Width High
80
ns
t
SCLKL
SCLK Pulse Width Low
80
ns
T
LRSU
LRCK Setup Time before
SCLK rising edge
80
ns
T
LRHD
LRCK Hold Time after SCLK
rising edge
80
ns
t
SDSU
SDI setup time before SCLK
rising edge
25
ns
t
SDHD
SDI hold time after SCLK
rising edge
25
ns
t
SDOD
SDO Delay from SCLK falling
edge
25
ns
t
JITTER
Jitter of LRCK
internal PLL generates MCLK from
LRCK
-20
20
ns
I2S direct mode
T
SCD
SCLK delay after MCLK
rising edge
0.5
1.5
ns
T
LRD
LRLCK delay after SCLK
rising edge
0.5
1.5
ns
t
SDSU
SDI setup time before SCLK
rising edge
5
ns
t
SDHD
SDI hold time after SCLK
rising edge
5
ns
t
SDOD
SDO Delay from SCLK falling
edge
15
ns