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Revision 1.10
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AS3542 3v2
Data Sheet, Strictly Confidential - D e ta i l e d D e s c r i p t i o n - A u d i o F u n c t i o n s
8.5.3 I2S
Modes
The AFE can be operated either in Slave Mode or in Slave Mode with the master clock directly signalled via pin MCLK.
The master clock (MCLK) is the necessary internal over-sampling clock for the DAC and ADC (e.g. 128*fs, fs=audio
sampling frequency)
In Slave Mode the PLL generates the master clock based on LRCK. Thus the PLL needs to be preset to the expected
sampling frequency. The ranges are 8kS-23kS (8kHz-23kHz) and 24kS-48kS (24kHz-48kHz). Please refer to register
1A-7h.
Figure 11. I2S Modes
8.5.4 Clock
Supervision
The digital audio interface automatically checks the LRCK. An interrupt can be generated when the state of the LRCK
input changes. A bit in the interrupt register represents the actual state (present or not present) of the LRCK.
8.5.5 Signal
Description
The digital audio interface uses the standard I2S format:
left justified
MSB first
one additional leading bit
The on-chip synchronization circuit allows any bit-count up 32bit. When there are less than 18 bits sampled, the data
sample is completed with “0”s. In I2S direct mode the data length has to be minimum 18 bits.
The ADC output is always 14 bit. If more SCLK pulses are provided, only the first 14 will be significant.
SCLK has not to be necessarily synchronous to LRCK but the high going edge has to be separate from LRCK edges.
The LRCK signal has to be derived from a jitter-free clock source, because the on-chip PLL is generating a clock for
the digital filter, which has to be always in correct phase lock condition to the external LRCK.
Please observe that LRCK has to be activated before enabling the ADC.
Figure 12. I2S left justified mode