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AVR1612 

8282A-AVR-11/10 

3.2 Enable the PDI module 

The PDI Physical must be enabled before it can be used. This is done by first forcing 
the PDI_DATA line high for a period longer than the equivalent external reset 
minimum pulse width (refer to device data sheet for reset characteristics). 

The first PDI_CLK cycle must start no later than 100µS after the RESET functionality 
of the Reset pin was disabled. If this does not occur in time the RESET functionality 
of the Reset pin is automatically enabled again and the enabling procedure must start 
over again. 

After this sequence, the PDI is enabled and ready to receive instructions. The enable 
sequence is shown in 

Figure 3-2

Figure 3-2. 

Sequence for enabling the PDI.

 

 

3.3 Enter external programming mode 

Even after an external programmer has established communication with the PDI 
module, the internal interfaces are not accessible by default. To get access to the 
NVM Controller and the NVM memories for programming, a unique key must be 
signalized by using the KEY instruction. The internal interface is accessed as one 
linear address space using a dedicated bus (PDIBUS) between the PDI and the 
internal interfaces. 

PDI Control and Status Register Space can be accessed with STCS (Store) and 
LDCS (Load) instruction. Please refer to “29.7 Register Description - PDI Control and 
Status Register” section and “29.5.7 Instruction Set Summary” section of th for more information. 

The key that must be sent using the KEY instruction is 64 bits long. The key that will 
enable NVM Programming is: 

0x1289AB45CDD888FF 

The sequence of entering external programming is as following: 

1.  Load the PDI RESET register with the Reset Signature (0x59). 
2.  Load the correct NVM key in the PDI. 
3.  Poll NVMEN in the PDI Status Register (PDI STATUS) until NVMEN is set. 

When the NVMEN bit in the PDI STATUS register is set the NVM interface is active 
from the PDI. 

3.4 Memory Programming 

This section describes how to program the Non Volatile Memory (NVM) in XMEGA

®

 

with external programming. The NVM consist of the Flash Program Memory, User 
Signature and Calibration rows, Fuses and Lock Bits, and EEPROM data memory. 

For external programming the device is accessed through the PDI and PDI Controller, 
using PDI physical connection. Through the PDI, the external programmer access all 

Summary of Contents for AVR1612

Page 1: ...NVM Controller trough the PDI interface and executing NVM Controller commands The PDI is a 2 pin interface using the Reset pin for the clock input PDI_CLK and the dedicated pin for data input and out...

Page 2: ...scribes the PDI serial frame format Figure 2 1 PDI serial frame format 2 2 Serial transmission and reception The PDI physical layer is either in Transmit TX or Receive RX mode of operation By default...

Page 3: ...1287 ATXmega128A1 XCK RXD TXD 220R 220R PDI CLK PDI DATA 2 4 PDI instruction set The PDI has a small instruction set that is used for all access to the PDI itself and to the internal interfaces All in...

Page 4: ...D 0x20 Load data from PDIBUS Data Space using indirect addressing ST 0x60 Store data to PDIBUS Data Space using indirect addressing LDCS 0x80 Load data from PDI Control and Status Register Space STCS...

Page 5: ...refer to 29 5 7 Instruction Set Summary section of the XMEGA A MANUAL for more information 2 5 NVM Commands The NVM commands that can be used for accessing the NVM memories from external programming a...

Page 6: ...rite Boot Loader Section Page PDI Write 0x39 Boot Loader Section CRC NVMAA Calibration and User Signature sections 0x03 Read User Signature Row PDI Read 0x18 Erase User Signature Row PDI Write 0x1A Wr...

Page 7: ...hould be removed if PDI programming and debugging is used Other external reset sources driving this line should be disconnected Any load on the clock line may give a delay on the clock edge that cause...

Page 8: ...is accessed as one linear address space using a dedicated bus PDIBUS between the PDI and the internal interfaces PDI Control and Status Register Space can be accessed with STCS Store and LDCS Load ins...

Page 9: ...Bus Doing this all data and program memory spaces are mapped into the linear PDI memory space Figure 3 3 shows the PDI memory space and the base address for each memory space in the Atmel ATxmega128A...

Page 10: ...e data in the Flash or EEPROM page buffer the Flash or EEPROM page must be erased Programming an un erased Flash or EEPROM Page will corrupt the content in the Flash or EEPROM Page 1 Erase Flash or EE...

Page 11: ...the selected fuse or Lock Bits by doing a PDI Write operation The BUSY flag in the NVM STATUS register will be set until the command is finished For lock bit write the LOCK BIT write command can also...

Page 12: ...until it has been cleared Erase and program the EEPROM memory 1 Erase the flash page buffer i Use the ST ptr command to set the address 0x00000000 ii Write Erase EEPROM Page Buffer 0x36 command to th...

Page 13: ...this layer 2 The high level target XMEGA NVM driver which interface the low level PDI driver 3 The low level PDI driver uses the reduced instructions set for the PDI interface to communicate with the...

Page 14: ...tion can be used here used C xplain_pdi_prog 4 Open either the GCC project file or the IAR project file and compile the source code 5 Connect the USB cable of Atmel Xplain to provide power to the Xpla...

Page 15: ...AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODU...

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