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10 

AVR1612 

8282A-AVR-11/10 

3.4.1 Chip Erase 

The Chip Erase command is used to erase the Flash Program Memory, EEPROM 
and Lock-Bits. The User Signature Row, Calibration Row and Fuses are not affected. 

The Chip Erase sequence is as below: 

1.  Load the NVM CMD register with Chip Erase command (refer to 

Table 2-2

). 

2.  Set the CMDEX bit in NVM CTRLA register. 

NOTE 

The Chip Erase command disables the PDI controller and the NVM. Poll the NVMEN 
bit until this is set, indict the PDI controller is enabled. 

3.4.2 Program Flash and EEPROM Page 

Flash and EEPROM page programming is done by first filling the associated page 
buffer, and then writing the entire page buffer to a selected page in Flash or 
EEPROM. 

The size of the page buffers depend on the Flash and EEPROM size in each device, 
and details on page size and page number is described in each device data sheet. 

3.4.2.1 Flash and EEPROM Programming Sequence 

Before programming a Flash or EEPROM page with the data in the Flash or 
EEPROM page buffer, the Flash or EEPROM page must be erased. Programming an 
un-erased Flash or EEPROM Page will corrupt the content in the Flash or EEPROM 
Page. 

1.  Erase Flash or EEPROM Page Buffer. 
2.  Load the Flash or EEPROM Page Buffer. 
3.  Perform a Page Erase and Write. 

3.4.2.2 Erase Page Buffer 

The Erase Flash Page Buffer and Erase EEPROM Page Buffer commands are used 
to erase the Flash and EEPROM page buffers. 

1.  Load the NVM CMD register with the Erase Flash/EEPROM Page Buffer 

command. 

2.  Set the CMDEX bit in the NVM CTRLA register. This requires the timed CCP 

sequence during self-programming. 

The BUSY flag in the NVM STATUS register will be set until the operation is 
completed. 

3.4.2.3 Load Page Buffer 

The Load Flash Page Buffer and Load EEPROM Page Buffer commands are used to 
load one byte of data into the Flash and EEPROM page buffers. 

1.  Load the NVM CMD register with the Load Flash/EEPROM Page Buffer 

command. 

2.  Write the selected memory address by doing a PDI Write operation. 

Since the Flash page buffer is word accessing and the PDI uses byte addressing, the 
PDI must write the Flash Page Buffer in correct order. 

Summary of Contents for AVR1612

Page 1: ...NVM Controller trough the PDI interface and executing NVM Controller commands The PDI is a 2 pin interface using the Reset pin for the clock input PDI_CLK and the dedicated pin for data input and out...

Page 2: ...scribes the PDI serial frame format Figure 2 1 PDI serial frame format 2 2 Serial transmission and reception The PDI physical layer is either in Transmit TX or Receive RX mode of operation By default...

Page 3: ...1287 ATXmega128A1 XCK RXD TXD 220R 220R PDI CLK PDI DATA 2 4 PDI instruction set The PDI has a small instruction set that is used for all access to the PDI itself and to the internal interfaces All in...

Page 4: ...D 0x20 Load data from PDIBUS Data Space using indirect addressing ST 0x60 Store data to PDIBUS Data Space using indirect addressing LDCS 0x80 Load data from PDI Control and Status Register Space STCS...

Page 5: ...refer to 29 5 7 Instruction Set Summary section of the XMEGA A MANUAL for more information 2 5 NVM Commands The NVM commands that can be used for accessing the NVM memories from external programming a...

Page 6: ...rite Boot Loader Section Page PDI Write 0x39 Boot Loader Section CRC NVMAA Calibration and User Signature sections 0x03 Read User Signature Row PDI Read 0x18 Erase User Signature Row PDI Write 0x1A Wr...

Page 7: ...hould be removed if PDI programming and debugging is used Other external reset sources driving this line should be disconnected Any load on the clock line may give a delay on the clock edge that cause...

Page 8: ...is accessed as one linear address space using a dedicated bus PDIBUS between the PDI and the internal interfaces PDI Control and Status Register Space can be accessed with STCS Store and LDCS Load ins...

Page 9: ...Bus Doing this all data and program memory spaces are mapped into the linear PDI memory space Figure 3 3 shows the PDI memory space and the base address for each memory space in the Atmel ATxmega128A...

Page 10: ...e data in the Flash or EEPROM page buffer the Flash or EEPROM page must be erased Programming an un erased Flash or EEPROM Page will corrupt the content in the Flash or EEPROM Page 1 Erase Flash or EE...

Page 11: ...the selected fuse or Lock Bits by doing a PDI Write operation The BUSY flag in the NVM STATUS register will be set until the command is finished For lock bit write the LOCK BIT write command can also...

Page 12: ...until it has been cleared Erase and program the EEPROM memory 1 Erase the flash page buffer i Use the ST ptr command to set the address 0x00000000 ii Write Erase EEPROM Page Buffer 0x36 command to th...

Page 13: ...this layer 2 The high level target XMEGA NVM driver which interface the low level PDI driver 3 The low level PDI driver uses the reduced instructions set for the PDI interface to communicate with the...

Page 14: ...tion can be used here used C xplain_pdi_prog 4 Open either the GCC project file or the IAR project file and compile the source code 5 Connect the USB cable of Atmel Xplain to provide power to the Xpla...

Page 15: ...AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODU...

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