6
6255B–ATARM–26-Jun-09
Application Note
4.4
Address (ALE = 1, CLE = 0)
Addresses are written to the address register on the rising edge of WE# when:
• CE# and CLE are low
• ALE is high
Addresses are input on I/O[7:0] only. For devices with a x16 interface, I/O[15:8] must be written
with zeros when issuing an address. Generally all five ADDRESS cycles are written to the
device.
4.5
Data (ALE = 0, CLE = 0)
Data is written to the data register on the rising edge of WE# when CE#, CLE, and ALE are low.
Data is input on I/O[7:0] for x8 devices, and I/O[15:0] on x16 devices.
4.6
Ready / Busy
The R/B# output provides a hardware method of indicating the completion of a PRO-
GRAM/ERASE/READ operation. The signal is typically high, and transitions to low after the
appropriate command is written to the device. A dedicated PIO should be assigned to this signal
with a pull-up resistor for proper operation. Alternatively, the READ STATUS command can be
used by the software.
4.7
Example
The following waveforms shows the successive accesses: COMMAND Latch, ADDRESS Latch
and DATA Output with a “CE don’t Care” NAND. Notice that no command can be sent to the
NAND Flash during tR, because it is busy.
Figure 4-1.
Page READ Operation
