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6255B–ATARM–26-Jun-09
Application Note
Important Note:
Any intentional erasure of the original invalid block information is prohibited.
3.3
ECC
NAND devices are subject to data failures that occur during device operation. To ensure data
read/write integrity, system error-checking and correction (ECC) algorithms must be imple-
mented. Depending on the AT91 product, the ECC algorithm must be calculated by software or
can be generated by the embedded hardware ECC controller. The ECC controller is capable of
single bit error correction and 2-bit random detection. When NAND has more than 2 bits of
errors, the data cannot be corrected. This controller allows ECC management without CPU inter-
vention and thus improves the total bandwidth of the system.
4. NAND Flash Signals
4.1
Bus Operation
The bus on NAND Flash devices is internally multiplexed. Data I/O, addresses, and commands
all share the same pins. I/O pins. I/O[15:8] are used only for data in the x16 configuration.
Addresses and commands are always supplied on I/O[7:0].
The command sequence normally consists of a command latch cycle, an ADDRESS LATCH
cycle, and a DATA cycle — either READ or WRITE.
4.2
Control Signals
The signals CE#, WE#, RE#, CLE and ALE control Flash device READ and WRITE operations.
CE# is used to enable the device. When CE# is low and the device is not in the busy state, the
Flash memory accepts command, data, and address information.
When the device is not performing an operation, the CE# pin is typically driven HIGH and the
device enters standby mode. The memory enters standby if CE# goes HIGH while data is being
transferred and the device is not busy.
A subset of NAND Flash supports the CE# “Don’t Care” operation allowing the NAND Flash to
reside on the same asynchronous memory bus as other Flash or SRAM devices. Other devices
on the memory bus can then be accessed while the NAND Flash is busy with internal opera-
tions. This capability is important for designs that require multiple memory devices on the same
bus.
4.3
Commands (ALE = 0, CLE = 1)
All the NAND operations (except READ STATUS and RESET commands) consist of a com-
mand write cycle followed by address write cycle. The READ STATUS command does not have
an address write cycle. The command is transferred into the NAND command register followed
by the start address, for the read or program operation, latched into the address register.
Commands are written to the command register on the rising edge of WE# when:
• CE# and ALE are low
• CLE is high
Commands are input on I/O[7:0] only. For devices with a x16 interface, I/O[15:8] must be written
with zeros when issuing a command.
