Artesyn PCIE-7210-2-32GB, Installation And Use Manual, Page: 42 / 82

Functional Description
42 SharpStreamer
TM
Pro Installation and Use (6806800V01B)
3.10 Clock Distribution
Clocking for each CPU complex consists of two input crystals. One 24 MHz crystal to drive all
the main buses and a 32.768 kHz crystal to drive the real time clock. Processor clocks are driven
from the PCH device. Each CPU has a dual channel memory, each memory channel provides an
1066.67 MHz clock to their respective memory channel.
3.11 Reset Management
Each PCH reset is controlled by the CPLD. CPU and peripheral reset are controlled by the PCH.
During power up the CPLD state machine drives the reset control to each CPU during an
induced reset from the front panel reset switch.
For more information about Reset button, refer the section Controls on page58 .
3.12 JTAG
The PCIe slot JTAG pins are mapped to the CPLD JTAG programming pins.

CPLD programming port at connector P2 (Independent connector for CPLD)

Processor and PCH JTAG pins are connected to XDP connector
Figure 3-3. Location of Temperature Sensors - Secondary Side
U68 Temperature Sensor
U91 Temperature Sensor